Behavioral VHDL - Module 3
Table of Contents
Behavioral VHDL - Module 3
Outline
RASSP Roadmap
Module Goals
Introduction to Behavioral Modeling in VHDL
Example Behavioral VHDL Model
VHDL Processes
Process Syntax
Let's write a VHDL Model
Full Adder Architecture
Two Full Adder Processes
Complete Architecture
Alternate Carry Process
VHDL Sequential Statements
A Design Example - 2-bit Counter
The Wait Statement
Equivalent Processes
"wait until" and "wait for"
Mix and Match
Testbench
Things That Look Alike
Even Signal Assignment Statement
Signal Assignment Statements
Inertial vs Transport Delays
Subprograms
Functions
Functions (cont. 1)
Procedures
Procedure (cont. 1)
Bus Resolutions: Smoke Generator
Bus Resolution Functions
Bus Resolution: Smoke Generator Fixed
Null Transactions
Entity Statements
Blocks and Guards
VHDL Packages
Potential Problems To Avoid
Potential Problems to Avoid (cont. 1)
Resolving Difficulties
Case Study of the SDSP Microprocessor Organization
SDSP Microprocessor Instruction Architecture
SDSP Context and Clock
SDSP Bus Read Timing
SDSP Bus Write Timing
VHDL Models of the SDSP Microprocessor
Organization of the SDSP VHDL Model
The SDSP Testbench
Testbench Body
The SDSP Behavioral Model
The SDSP Read Memory Procedure
SDSP Write Memory Procedure
SDSP Add Procedure
SDSP Behavioral Model
The SDSP Clock Model
SDSP Memory Model
Exercising the SDSP Model
SDSP Benchmark
SDSP Benchmark
SDSP Benchmark
SDSP Benchmark
Summary
References
