VHDL Processes

A VHDL process statement is used for all behavioral descriptions
Example simple VHDL process

ARCHITECTURE behavioral OF clock_component IS
BEGIN
    PROCESS
      VARIABLE periodic: BIT := '1';
        BEGIN
         IF en = '1' THEN
            periodic := not periodic;
         END IF;
         ck <= periodic;
         WAIT FOR 1 us;
    END PROCESS;
END behavioral;