VHDL Sequential
Statements
Assignments executed sequentially in processes
Sequential statements
{
Signal
,
variable
} assignments
Flow control
if
<condition> then <statements> else <statements> end if;
for
<range> loop <statements> end loop;
while
<condition> loop <statements> end loop;
case
<condition> is when <value> => <statements>;
when <value> => <statements>;
when others => <statements>;
end case;
Wait
on <signal> until <expression> for <time>;
Assert
<condition> report <string> severity <level>;
