System Level VHDL - Module 4
Table of Contents
System Level VHDL - Module 4
Outline
RASSP Roadmap
Module Goals
Introduction - What do we mean by "System Modeling"
Describing RASSP Systems
Advantages of using VHDL
Types of System Models
Styles and Approaches
Models
Evolution of Approaches
System Level VHDL Constructs
Aliases
An Example
Foreign Interfaces
An Example
TEXTIO
TEXTIO Procedures
Using TEXTIO
An Example
Assert Statements
Assert Statements
An Example
Abstract Data Types
An Example
Example Use of QUEUE ADT
Queue System VHDL Model
Queue Example Declarations
Queue Example Declarations 2
Architecture Body
Queue Example: Architecture Body 2
Shared Variables
Non-determinism
Stack Example
Stack Example 2
Records
Data Types
Advantages of Object Oriented VHDL
Advantages of OO-VHDL 2
Advantages of OO-VHDL 3
Advantages of OO-VHDL 4
Advantages of OO-VHDL 5
Advantage of OO-VHDL 6
Advantages of OO-VHDL 7
Advantages of OO-VHDL 8
Synthesizing OO-VHDL
Converting OO-VHDL to Synthesizable VHDL
Applications of System Level VHDL
UVA ADEPT Primitive Modules
Token Handling
ADEPT Token Handling
Basic Module Format: Packages and Entity
Basic Module Format: Architecture
Basic Module Format: Architecture
Three Module Example
Bus Resolution
Three Module Example: Simplified Event Sequence
Three Module Example: Detailed Event Sequence
Honeywell PML
Token Type
Handshaking Protocol
Bus Resolution
Bus Resolution Code
Idle State
Request State
Ack State
Busy State
Bus Interface Unit
Use of BIU
Functional Memory Component
Functional Memory Interface
Steps to Set-up the Functional Memory
Functional Memory Operations
More Functional Memory
Summary
References
