Converting OO-VHDL to
to Synthesizable VHDL
Remove any reliance on the message queue
Immediate
messages,
select
and
accept
statements
Remove any hierarchy-spanning messages
A
component
should only communicate with parent, child, or sibling
Convert the messaging protocol to a signaling protocol
Convert operations to subprograms
Convert instance
variables
to
signals
or variables, as appropriate
Add a clock
