Signal Documentation of VHDL Codes for DLX

Following is a list of VHDL codes for DLX whose signal documentation is povided:

  • add_cla.vhd
  • addsub_cla.vhd
  • and2_g.vhd
  • clock2xgen.vhd
  • clockdrv.vhd
  • control.vhd
  • cp1_cntl.vhd
  • decode.vhd
  • define.vhd
  • delayline.vhd
  • dlx.vhd
  • dlxalu.vhd
  • dlxalu_logic.vhd
  • dlxregfile.vhd
  • dlxregs.vhd
  • dlxregs_misc.vhd
  • dlxutils.vhd
  • dualport.vhd
  • execute.vhd
  • fetch.vhd
  • interrupt.vhd
  • mdr.vhd
  • mem.vhd
  • memoryD.vhd
  • memoryI.vhd
  • mux2_g.vhd.html
  • not_g.vhd
  • pc.vhd
  • pc_control.vhd
  • reg32x32.vhd
  • rfglue.vhd
  • rfglueall.vhd
  • rfwrite.vhd
  • write_dlx.vhd
  • xnor2_g.vhd