dlxalu.vhd

This code basically contains two blocks in the ALU module.They are the dlxalu_logic block that contains the logic for all the alu operations and the addsub_cla block which is an adder/subtractor

S1bus

Output bus of the A register

S2bus

Output bus of the B register

AlUop

Describes the ALU operation to be performed e.gadd,sub etc

LMDRbus

Output bus of the LMD register

Destbus

Current output of the ALU

Destbus_a & Destbus_b

The output of the ALU at the memory stage and the write back stage respectively.

S1select

Mux select to select the S1_internal value

S2select

Mux select to select the S2_internal value

add_a,add_b

The two inputs to the adder
adsub = 0 indicates an add operation
addsub = 1 indicates a subtract operation