dlxalu_logic.vhd
This code gives the logic for the ALU block of the DLX
S1bus
Output bus of the A register
S2bus
Output bus of the B register
AlUop
Describes the ALU operation to be performed e.gadd,sub
etc
LMDRbus
Output bus of the LMD register
Destbus_a & Destbus_b
The output buses of the ALU
S1select
Mux select to select the S1_internal value
S2select
Mux select to select the S2_internal value
add_a, add_b
The two inputs to the adder
adsub = 0 indicates an add operation
addsub = 1 indicates a subtract operation
shift_count
It gives the amount of shift