The Array
The XC2S300e has 16 block RAMs. These can be configured into a 16 port non blocking RAM array.
The idea is to assign one block to each CPU, but allow other CPUs to write into the memory on a prioritised basis.
Block RAM Array
The block RAMs are 256 x 16 bits.
Each RAM will have a 16 input 8 bit address bus multiplexer connecting to each of the procesors.
Each RAM will also have a 16 input 16 bit data bus multiplexer connected to each processor
Each processor will have a 16 input 16 bit data bus multiplexed connected to each block RAM output.
The Block RAMs will be dual ported so they can be mapped into the host processors memory map.
RAM Access Arbitration
The Micro16 addresses 4K words of memory so the top 4 address bits can be used to select the memory bank.
The high order CPU address bus can be used to arbitrate access to each of the block RAMs.
If there there is a conflict in access to a block of memory, the CPU with the highest CPU address will win out.
this means that the processors that are sending a message have priority
over the CPU that accesses that block of memory at a lower address. The
higher the RAM appears in the CPU map, the higher the priority the CPU
has to gain access to that memory. There will be an arbitrator for each
block of memory that will hold all but the higehest priority CPU.
Each CPU requires an acknowledge to its access strobe before it can
continue. the bus arbitrator will simply hold off lower priority CPU's.
Address translation
Because each processor resets at location 000H, there must be an address translation table on the high order 4 bits
that allows each CPU to address it's own 256 byte block of RAM. This
will also assign the priority of the CPU over a neighbours resources.
The address translation table will be set up by the host CPU while the
Slave CPU is held in Reset.
The higher the address, the higher the priority the CPU has to another CPU's memory.
FPGA resources
The Micro16 CPU uses about 7% of a XC2S300e.
This means you can implement about 14 CPU's however the address and data multiplexers will eat into this figure.
The host CPU will have to be in a separate FPGA.
Interprocessor Messaging
Each Micro16 has an interrupt input.
It is invisaged that this interrupt line will be activated each time another CPU writes into it's memory.
The interrupt routine can transfer the message passed and acknowledge receipt of the message to the sending CPU.
Host CPU
The host processor will have control over the reset lines to each CPU
and can configure the address translation table for each CPU. It will
also be able to load program code into each of the Slave CPU's dual
port memory, ready for execution.
I plan using
System09 on my old B3 FPGA board:
B3 Connector J4 is wired to B5-X300 Connector H
B3 Connector J3 is wired to B5-X300 Connector G
B3 Connector J6 connects to Modified B3-SRAM
B3 Connector J9 connects to Modified B3-SRAM
B3 Connector J11 is used for a dual 8 bit parallel I/O port
B3 Connector J10 is reserved for the Test button and LED
B3 Connector J8 connects to the CPU Peripheral IO board
B3 Connector J5 (printer port) in not used.
System09 maps the bus interface via the DAT memory space ...
$00000 - $3FFFF maps to the B3-SRAM module
$40000 - $FFFFF maps to the B5-X300 board.
A "bus_csn" (inverted chip select) and "bus_hold" signal can be used to insert wait states.
The host processor board system clock must be configured for 25 MHz
operation but the CPU clock is 12.5 MHz. The CPU clock is distributed
to the B5-X300 board via the connectors.