Basic VHDL - Module 1
Table of Contents
Basic VHDL - Module 1
Outline
RASSP Roadmap
Module Goals
Introduction - The Need for Education
Putting It All Together
Concepts and History of VHDL
History of VHDL
Why Use VHDL?
Gajski and Kuhn's Y Chart
Sample VHDL Design Process
Behavioral Specification
Data Flow Specification
Structural Specification
VHDL Models of Hardware
Behavioral Model
Structural Model
Timing Model
Delay Types
Inertial Delay
Transport Delay
Delta Delay
Example Without Delta Delay
Delta Delay
Example With Delta Delay
VHDL Basics
Data Types
Scalar Types
Scalar Types 2
Scalar Types 3
Scalar Types 4
Scalar Types 5
Composite Types 1
Composite Types 2
Composite Types 3
Access Types
Subtypes
Summary
Objects
Constants
Scoping Rules
Variables
Signals
Signals vs Variables
Signals vs Variables (Cont. 1)
Signals vs Variables (Cont. 2)
Sequential and Concurrent Statements
Sequential Statements
Concurrent Statements
Assignments
Sequential Signal Assignments
Entity and Architecture Declarations
Port Declaration
Name
Port Mode
Port Mode Examples
Type of Data
Entity Declarations
Architecture Declarations
Packages and Libraries
Packages
Declaration
Package Body
Use Clause
Libraries
Attributes
Register Example
Register Example (cont. 1)
Register Example (cont. 2)
Predefined Operators
List of Operators
Some Explanations
Summary
Putting It All Together
References
