Exercises 9.




Q1 a) Determine the maximum frequency for the following circuit (to be drawn)

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t_Combinational= 24ns, ti_terconnect=4ns, t_setup = 3ns, t_hold= 2ns, t_cq= 5ns.

< P> < FONT size= +1> b) Break up the combination logic and introduce a pipeline and recalculate the frequency.

 

 


Q2. With reference to the following circuit(to be drawn) and for clock period of 50 ns and using delay values given in Q1 determine:











i) Setup time slack,
ii) Hold time slack
iii) Is there any timing violation?
iv) Draw timing diagram for CLK, CLK' , X, and Y.
v) If you had to improve the design how would you go about it.


Q3 For the Finite State Machine below determine the maximum operating speed.