Exercises 8.
Q1- The following model uses an embedded for generate statements to describe a
two-dimensional structure.
entity LOGIC is
port (A,B : in BIT_VECTOR (3 downto 0); X : out BIT);
end LOGIC;
architecture STRUCTURE of LOGIC is
component AND_GATE
port (A,B : in BIT; Z : out BIT); end component;
component OR_2
port ( A,B : in BIT; Z : out BIT ); end component;
signal ASIG, OSIG : BIT_VECTOR (3 downto 0) := X\'0\';
begin
R: for COL in 1 to 2 generate
C: for ROW in 3 downto 0 generate
R1: if CCOL=1) generate
AX: AND_GATE port map (A(ROW), B(ROW), ASIG (ROW));
end generate R1;
R1C: if (COL=2 and ROW /=0) generate
OX: OR2_GATE port map (ASIG(ROW), OSIG(ROW), OSIG(ROW-1);
end generate R1C;
R1C0: if (COL=2 and ROW=0 ) generate
O0: OR2_GATE port map ( ASIG(ROW), OSIG), X);
end generate R1C0;
end generate C; end generate R;
end STRUCTURE;
a) Draw the logic diagram described by the VHDL model.
b) Generate the logic expression for X= F(A,B).
c) Under what set of input condition is the output X asserted active-1?