Exercises 7.

Q1- Write a VHDL code to model a Full-Adder at the algorithmic level. a) write all the necessary library and package statement required. b) Analyze the entity using SYNOPSIS. c) Write a test bench and integrate it on top of the design d) Simulate the entity using SYNOPSIS.

Q2. Convert your design to a structural design, declaring all components used (as sume components have zero delay). a) Analyze your design. b) Simulate your design. c) Change components characteristics to have time delay and re-analyze and simu late your circuit.

Q3. Using the process and the generate statements design a four bit carry propa gate adder, together with a test bench . Analyze and simulate your design.