Exercises 12.
Q1. For the self timed circuit shown below(drawn in class) make the following as
sumptions. The propagation through the NAND gate can be 5ns, 10ns, or 20ns with
equal probability. The logic in the succeeding stages is such that the second stage is
always ready for data from the first circuit.
a) Calculate the average propagation delay with ths=6ns.
b) calculate the average propagation delay with ths=12ns
c) If the handshaking circuitry is replaced by a synchronous clock, what is the
smaller possible clock frequency?
d) A DCVSL NAND gate is given below, use it with a muller element to design the
circuit.