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A body associated with an entity declaration to describe the internal organization or operation of a design entity. An architecture body is used to describe the behavior, data flow, or structure of a design entity.
architecture architecture_name of entity_name is
architecture_declarations
begin
concurrent_statements
end [ architecture ] [ architecture_name ];
Architecture assigned to an entity describes internal relationship between input and output ports of the entity. It consists of two parts: declarations and concurrent statements.
First (declarative) part of an architecture may contain declarations of types, signals, constants, subprograms (functions and procedures), components, and groups. See respective topics for details.
Concurrent statements in the architecture body define the relationship between inputs and outputs. This relationship can be specified using different types of statements: concurrent signal assignment, process statement, component instantiation, concurrent procedure call, generate statement, concurrent assertion statement and block statement. It can be written in different styles: structural, dataflow, behavioral (functional) or mixed.
The description of a structural body is based on component instantiation and generate statements. It allows to create hierarchical projects, from simple gates to very complex components, describing entire subsystems. The connections among components are realized through ports. Example 1 illustrates this concept for a BCD decoder.
The Dataflow description is built with concurrent signal assignment statements. Each of the statements can be activated when any of its input signals changes its value. While these statements describe the behavior of the circuit, a lot of information about its structure can be extracted form the description as well. Example 2 contains this type of description for the same BCD decoder as in the previous example.
The architecture body describes only the expected functionality (behavior) of the circuit, without any direct indication as to the hardware implementation. Such description consists only of one or more processes, each of which contains sequential statements (Example 3).
The architecture body may contain statements that define both behavior and structure of the circuit at the same time. Such architecture description is called mixed (Example 4).
Example 1
architecture Structure of
Decoder_bcd is
signal S: Bit_Vector(0 to 1);
component AND_Gate
port(A,B:in
Bit; D:out Bit);
end component;
component Inverter
port(A:in
Bit; B:out Bit);
end component;
begin
Inv1:Inverter
port map(A=>bcd(0),
B=>S(0));
Inv2:Inverter
port map(A=>bcd(1),
B=>S(1));
A1:AND_Gate
port map(A=>bcd(0),
B=>bcd(1), D=>led(3));
A2:AND_Gate
port map(A=>bcd(0),
B=>S(1), D=>led(2));
A3:AND_Gate
port map(A=>S(0),
B=>bcd(1), D=>led(1));
A4:AND_Gate port map(A=>S(0),
B=>S(1), D=>led(0));
end Structure;
The components Inverter and AND_Gate are instantiated under the names
Inv1, Inv2, A1, A2, A3 and A4. The connections among the components
are realized by the use of signals S(0), S(1) declared in the
architecture's declarative part.
Example 2
architecture Dataflow of
Decoder_bcd is
begin
led(3) <= bcd(0) and bcd(1);
led(2) <= bcd(0) and
(not bcd(1));
led(1) <= (not
bcd(0)) and bcd(1);
led(0) <= (not
bcd(0)) and (not bcd(1));
end Dataflow;
All the four statements here are executed concurrently and each of
them is activated individually when any of its input signals changes
its value.
Example 3
architecture procedural of
Decoder_bcd is
signal S: bit_vector (3 downto 0);
begin
P1: process
(bcd, S)
begin
case
bcd is
when
"00" => S <= "0001" after
5 ns;
when
"01" => S <= "0010" after
5 ns;
when
"10" => S <= "0100" after
5 ns;
when
"11" => S <= "1000" after
5 ns;
end case;
led <= S;
end process;
end procedural;
The clause "after 5 ns" here allows to introduce time delay
of the circuit. The assignment of a new value to the led signal will
be done only after 5 nanoseconds of the simulated time.
Example 4
architecture Mixed of
Decoder_bcd is
signal S: Bit_Vector(0 to 2);
component Inverter
port(A: in
Bit; B: out Bit);
end component;
begin
Inv1: Inverter port map
(A=>bcd(0), B=>S(0));
Inv2: Inverter port map
(A=>bcd(1), B=>S(1));
P: process (S, bcd)
begin
led(0) <= S(0) and
S(1) after 5 ns;
led(1) <= S(0) and
bcd(1) after 5 ns;
led(2) <= bcd(0) and
S(1) after 5 ns;
led(3) <= bcd(0) and
bcd(1) after 5 ns;
end process;
end Mixed;
Above, two Inverter component instantiation statements define the
circuit responsible for determining the value of the signal S. This
signal is read by behavioral part i.e. the process statement P. In
this process, the values computed by the and operation are assigned
to the led output port.
Single entity can have several architectures, but architecture cannot be assigned to different entities.
Architecture may not be used without an entity.
All declarations defined in an entity are fully visible and accessible within each architecture assigned to this entity.
Different types of statements (i.e. processes, blocks, concurrent signal assignments, component instantiations, etc.) can be used in the same architecture.
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