Aliases

Aliases can significantly improve the readability of VHDL descriptions by using a shorthand notation for names

Aliases allow reference to named items in different ways:

SIGNAL data_word: mvl_vector(15 DOWNTO 0);
ALIAS data_bus: mvl_vector (7 DOWNTO 0) IS data_word (15 DOWNTO 8);

Aliases can rename any named item except labels, loop parameters, and generate parameters