Packages are made visible to a VHDL description through the use of the
use clause. This statement comes at the beginning of the
entity or architecture file and makes the contents of a package
available within that file.
The USE clause can select all or only part of a particular
package. In the first example above, only the binary
data type and add_bits3 procedure are made visible. In the
second example, the full contents of the package are made
visible by use of the keyword ALL in the use clause.
