Micro8b - Proposed Enhancements new

I was thinking I'd do a Micro8B that had an 11 bit index register rather than 8 bit. I'd substitute the ADDX with LDX and NORX with CPX. I also want to add a JMP instruction, because position independant code is not possible if you want to jump to fixed library routines.
JSR's can be acheived with a BSR to a JMP instruction. I'd replace the conditional branches so they only branched on the TRUE condition of the condition codes and not false. ie BEQ but not BNE, BCS not not BCC etc. I'd also add a test for the Interrupt Flag, BIS. I'd do the tests for oposite conditions by conditionally branch around a BRA (Branch always) instruction.

I was wanting to introduce a LEAXP offset ie. load Index Register with the effective address formed by adding the PC to an offset. This is so I can index position independent data. What I ended up proposing is a TPX (Transfer PC to Index Register) and a LEAXX offset instruction. The CPXX (Compare Index Register Indexed), is a "do nothing" instruction so I have used that as an LEAXX instruction which is effectively ADDXI (Add Index Register Immediate). I also have an APX instruction (Add PC to Index register) so you can effectively acheive the same thing by preloading Index Register with the address of the data relative to the APX instruction.

 LDXI data - base
 APX
base: ADDAX #000
 INCX
 JMP somewhere
;
data: B (#55)
 B (#AA)

--- or ---

 TPX
base: LEAXX data - base
 ADDAX #000
 INCX
 JMP somewhere
;
data: B (#55)
 B (#AA)

STXX (store Index Register Indexed) is another "do nothing" instruction so I have re-instated some of the inherent intructions for the index register (INC, DEX, CLR, NEG, COM, TST) under that opcode. I've also added ADAX (Add Accumulator to index register). The shift instructions don't serve much purpose on an index register so I have dropped them.

I was also thinking I should make the ALU 12 bit, to accomodate the extended index register, and use the ALU to increment and decrement the Stack pointer and increment and load the Program counter. I could also use the ALU to calculate the Effective Memory Address for memory accesses. It should make the design  a little more efficient.

000 00 000 ADDI - Add Accumulator Immediate (followed by an 8 bit argument)
000 00 001 undefinded
000 00 010 INCA - Increment Accumulator
000 00 011 DECA - Decrement Accumulator
000 00 100 COMA - Complement Accumulator
000 00 101 NEGA - Negate Accumulator
000 00 110 TSTA - Test Accumulator
000 00 111 CLRA - Clear Accumulator
000 01 xxx ADDA - Add Accumulator Absolute
000 10 xxx ADDX - Add Accumulator Indexed
000 11 xxx ADDP - Add Accumulator PC Relative

001 00 000 NORI - NOR Accumulator Immediate (followed by an 8 bit argument)
001 00 001 ASRA - Arithmetic Shift Right Accumulator
001 00 010 ROLA - Rotate Left Accumulator
001 00 011 RORA - Rotate Right Accumulator
001 00 100 LSLA - Logical Shift Left Accumulator
001 00 101 LSRA - Logical Shift Right Accumulator
001 00 110 undefined
001 00 111 undefined
001 01 xxx NORA - NOR Accumulator Absolute
001 10 xxx NORX - NOR Accumulator Indexed
001 11 xxx NORP - NOR Accumulator PC Relative

010 00 000 RSP - Reset Stack pointer to #0FF
010 00 001 RTS - return from Subroutine
010 00 010 SWI - Software Interrupt
010 00 011 RTI - Return from interrupt
010 00 100 PSHX - Push Index Register onto the stack
010 00 101 PULX - Pull the Index register off the stack
010 00 110 PSHA - Push Accumulator onto the Stack
010 00 111 PULA - Pull Accumulator off the Stack
010 01 xxx STAA - Store Accumulator Absolute
010 10 xxx STAX - Store Accumulator Indexed
010 11 xxx STAP - Store Accumulator PC Relative

011 00 xxx BIS - Branch on Interrupt set
011 01 xxx BEQ - Branch if Equal (Zero Flag Set)
011 10 xxx BCS - Branch if Carry Set
011 11 xxx BMI - Bnanch if Minus (Negative Flag Set)

100 00 xxx LODXI - Add Index Register Immediate
100 01 xxx LODXA - Add Index Register Absolute
100 10 xxx LODXX - Add Index Register Indexed
100 11 xxx LODXP - Add Index Register PC Relative

101 00 xxx CMPXI - Compare Index Register Immediate
101 01 xxx CMPXA - Compare Index Register Absolute
101 10 xxx LEAXX - Load Index Register with Effective Indexed Address (ADDXI)
101 11 xxx CMPXP - Compare Index Register PC Relative

110 00 000 SEC - Set Carry Flag
110 00 001 CLC - Clear Carry Flag
110 00 010 SEI - Set Interrupt Flag
110 00 011 CLI - Clear Interrupt Flag
110 00 100 TPX - Transfer PC to Index Register
110 00 101 APX - Add PC to Index Register
110 00 110 TSX - Transfer SP to Index Register
110 00 111 TXS - Transfer Index Register to SP
110 01 xxx STOXA - Store Index Register Absolute
110 10 001 ADAX - Add Accumulator to Index Register
110 10 010 INCX - Increment Index Register
110 10 011 DECX - Decrement Index Register
110 10 100 COMX - Complement Index Register
110 10 101 NEGX - Negate Index Register
110 10 110 TSTX - Test Index Register
110 10 111 CLRX - Clear Index Register
110 11 xxx STOXP - Store Index Register PC Relative

111 00 xxx BSR - Jump Immediate would become BSR
111 01 xxx JMPA - Jump Absolute ( necessary for fixed library calls)
111 10 xxx JMPX - Jump Indexed (necessary for jump tables)
111 11 xxx JMPP - Jump PC relative is the same as BRA.

xxx Denotes the top order address bits of an 11 bit argument. The following byte forms the lower 8 bits of the argument.