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Altera Apex
Using Quartus 1999.10 and targeting an EP20K100E-1, v0.5 of the Free-6502 core took 2057 logic elements and ran at 28.16 MHz. This used a simple timing constraint of 25 MHz, so it is very likely that the design could be tweaked further to improve the speed.
This is a huge improvement over version 1999.06 of Quartus, which used 2683 logic elements and ran at 21.06 MHz-- with the same compiler settings. In addition, 1999.10 completed in roughly half the time that 1999.06 took.
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Xilinx Virtex-E
Using Foundation 2.1i-sp3 and targeting an XCV100E-8, of the Free-6502 v0.5 core took 557 slices and ran at 39 MHz. This used a simple clock period timing constraint of 39 MHz.
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AMI Semiconductor ASIC
Using Synopsis DC and targeting an AMI Semiconductor 0.6u gate array, the v0.3 of the Free-6502 core achieved:
Optimized for area: 3800 gates, 25 MHz
With timing constraints: 4200 gates, 50 MHz
With other timing constraints: 4800 gates, 60 MHz
These are pre-layout numbers.
The AMI Semiconductor numbers are courtesy of Ed Beers, Project Manager, Doctor Design Inc.
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TI GS20 ASIC
When targeted for TI's GS20 0.18 um process, v0.2 of the Free-6502 core took about 10k gates and ran at 166 MHz! This was using pre-layout numbers Synopsys DC Expert/Professional version 1999.05 and normal conditions (1.8v, 95º C).
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