Lab 2
Modeling of simple system
The purpose of this lab is to model quite simple system, which consists of some components. The behaviour of the system is the following. There are two bit sequences, which change their values only at the negative front of clock signal. There should be two counters, which summarize value of sequences at 2 previous clock cycles. System must consist of 3 parallel working components:
· Two similar modules, every count bits of its inputs and output number of bits at 2 previous clock cycles;
· adder, which outputs 1 if sum of bits number in sequences 1 and 2 equal to 3, otherwise outputs 0.
Example of realization:
Presented waveforms illustrate one possible realization, which consists of 4 parallel parts:
- Process which generates clock signal (clk of type bit) and input sequences (seq1 and seq2 of type bit_vector(1 downto 0)). Input sequences are valued at the negative front of clock signal. Sequences is the following:
seq1 11011000010110101001 and seq2 - 00111011000010110101
- Sub-module (finite state machine with two states), which summarize all ones in sequence 1 during last 2 clock cycles and output this value to cnt1 (cnt1 is of type bit_vector(1 downto 0))
- The second is the same component, the difference is input is seq2 and output is cnt2
- Dataflow command which outputs 1 if cnt1 and cnt2 in sum give 3.
The period of clock signal is 50 ns, the length of sequences is 20 bits, therefore for the simulation it is enough 1000 ns.
Requirements:
- Use types bit_vector
- Bit counters is easy to implement with the help of Moore finite state machine
- For comparison you can use the following structure:
sgn<= value1 when condition else value2 when condition2 else valueN;
Hints:
·
To save
sequence data you can use the following VHDL code:
constant seq1_arr: bit_vector (0 to 19) :=
"11011000010110101001";
·
To wait the
rising edge of clock signal you can use the following VHDL code:
wait until clk'event and clk='1';
·
For loops
in VHDL:
for i in a_arr'range loop
end loop;