© LRS - UNI Erlangen-Nuremberg
1.3.3 Clocked Process Simulation (3)
FSM is fed with asynchronous inputs (X); ONE state process
X can change together with clock edge
Physical world: STATE signal renewed before NEXTSTATE changes
RTL-Simulation:
Update
n
Update
n+1
STATE
CLK, ...
X, ...
F(STATE
old
, X
old
)
CLK, X, ...
...
F(STATE
old
, X
new
)
X, ...
CLK, ...
F(STATE
old
, X
new
)
© LRS - UNI Erlangen-Nuremberg © LRS - UNI Erlangen-Nuremberg
