library ieee;
use ieee.std_logic_1164.all;
use work.cypress.all;

entity ssncomb is

port
(
-- inputs
  signal  A:  in std_logic;  -- MSB
  signal  B:  in std_logic;  
  signal  C:  in std_logic;  
  signal  D:  in std_logic;  -- LSB
-- outputs
  signal    F1:  out std_logic;      
  signal    F2:  out  std_logic;                  
  signal    F3:  out std_logic;      
  signal    F4:  out std_logic
);

-- this pin assignment is specifically for 22V10!
attribute pin_numbers of ssncomb:entity is 
 "A:2 B:3  C:4  D:5 " &
  " F1:22   F2:21  F3:20  F4:19";  

end ssncomb;


--- STUDENTS: DO NOT MODIFY ANY STATEMENTS above this line

--*************************************************************************
-- Architecture body
--*************************************************************************

architecture a of ssncomb is

-- STUDENTS: If you want add temporary signals, put them here.
--


begin

--- STUDENTS: Put your statements starting on the next line



end a;