library ieee;
use ieee.std_logic_1164.all;
use work.cypress.all;

-- One-hot encoding  boolean solution for  SSN sequence
-- SSN = 458 70 2198
entity ssnseq is
  port (  clk,reset:  in std_logic;
	  odd: in std_logic;
	  qstate : out std_logic_vector(5 downto 0);
	  dout: out std_logic_vector(3 downto 0)
       );

-- this pin assignment is specifically for 22V10!
attribute pin_numbers of ssnseq:entity is 
 "clk:1 reset:2  odd:3  " &
  " dout(3):22   dout(2):21  dout(1):20  dout(0):19";  

end ssnseq;


architecture a of ssnseq is

-- change this to reflect the number of FFs you have
-- can have at MOST 6 FFs (5 downto 0) because 
-- 22V10 has only 10 output cells (each has a FF) and
-- four outputs are used for the "dout" signals

  signal q,d:  std_logic_vector(4 downto 0);

 
 begin


--- students: assign your external 'q' signals here
 qstate(5) <=  '0';  -- unused
 qstate(4) <= q(4);
 qstate(3) <= q(3);
 qstate(2) <= q(2);
 qstate(1) <= q(1);
 qstate(0) <= q(0);


-- State Flip Flops
  stateff: process (clk,reset)
   begin
   if (reset = '1') then
     q <= "00001";   -- students, change this your initial state
   elsif (clk'event and clk='1') then
     q <= d;
   end if;
  end process stateff;

--- next state equations here

 d(0) <= (q(4)) or (q(3) and odd);

 d(1) <= q(0);

 d(2) <= q(1);

 d(3) <= q(2);

 d(4) <= q(3) and (not odd);

--- output equations here

 dout(0) <= odd;

 dout(1) <= ((not odd) and q(3)) or
            (odd and q(1));

 dout(2) <= ((not odd) and q(0)) or
            (odd and q(0)) or
            (odd and q(1));


 dout(3) <= ((not odd) and q(1)) or
            ((not odd) and q(4)) or
            (odd and q(3));


 end a;