library ieee;
use ieee.std_logic_1164.all;
use work.cypress.all;

-- Mux block for ALU lab

entity smux4 is
  port (  a,b: in std_logic_vector(3 downto 0);
          s: in std_logic_vector(2 downto 0);
	  y: out std_logic_vector(3 downto 0)
       );


attribute pin_numbers of smux4:entity is

" a(3):2 a(2):3  a(1):4  a(0):5 b(3):6 b(2):7  b(1):8  b(0):9  s(2):15 s(1):14 s(0):13 " &
" y(3):22  y(2):21  y(1):20  y(0):19 ";  

end smux4;


architecture a of smux4 is

begin


 process

  begin
  
   case s  is
  
    when "000" => y <= a;
    when "001" => y <= not (a);
    when "010" => y <= b;
    when "011" => y <= not (b);
    when "100" => y <= "0000";
    when "101" => y <= "0000";
    when  others => y <= "1111";

   end case;

 end process;

end a;