library ieee;
use ieee.std_logic_1164.all;
use work.cypress.all;

-- 4 bit 2/1 Mux

entity mux4 is
  port (  a,b: in std_logic_vector(3 downto 0);
          s: in std_logic;
	  y: out std_logic_vector(3 downto 0)
       );


attribute pin_numbers of mux4:entity is

" a(3):2 a(2):3  a(1):4  a(0):5 b(3):6 b(2):7  b(1):8  b(0):9  s:10 " &
" y(3):22  y(2):21  y(1):20  y(0):19 ";  

end mux4;


architecture a of mux4 is

begin



  y <= b when (s = '0') else a;

end a;