| | | | | | | _________________ -| |- -| |- -| |- -| CYPRESS |- -| |- -| |- Warp VHDL Synthesis Compiler: Version 4 IR x95 -| |- Copyright (C) 1991, 1992, 1993, |_______________| 1994, 1995, 1996, 1997, 1998 Cypress Semiconductor | | | | | | | ====================================================================== Compiling: alu4.vhd Options: -d c22v10 -v1 -o2 -fo alu4.vhd ====================================================================== vhdlfe V4 IR x95: VHDL parser Wed May 9 15:44:03 2001 Library 'work' => directory 'lc22v10' Linking '/opt/ecad/warp/lib/common/work/cypress.vif'. Library 'ieee' => directory '/opt/ecad/warp/lib/ieee/work' Linking '/opt/ecad/warp/lib/ieee/work/stdlogic.vif'. vhdlfe: No errors. tovif V4 IR x95: High-level synthesis Wed May 9 15:44:03 2001 Linking '/opt/ecad/warp/lib/common/work/cypress.vif'. Linking '/opt/ecad/warp/lib/ieee/work/stdlogic.vif'. tovif: No errors. topld V4 IR x95: Synthesis and optimization Wed May 9 15:44:03 2001 Linking '/opt/ecad/warp/lib/common/work/cypress.vif'. Linking '/opt/ecad/warp/lib/ieee/work/stdlogic.vif'. ---------------------------------------------------------- Detecting unused logic. ---------------------------------------------------------- ------------------------------------------------------ Alias Detection ------------------------------------------------------ ------------------------------------------------------ Aliased 0 equations, 1 wires. ------------------------------------------------------ ---------------------------------------------------------- Circuit simplification ---------------------------------------------------------- ---------------------------------------------------------- Circuit simplification results: Expanded 0 signals. Turned 0 signals into soft nodes. Maximum expansion cost was set at 1. ---------------------------------------------------------- Created 20 PLD nodes. topld: No errors. ---------------------------------------------------------------------------- PLD Optimizer Software: DSGNOPT.EXE 11/NOV/97 [v4.02 ] 4 IR x95 DESIGN HEADER INFORMATION (15:44:03) Input File(s): alu4.pla Device : C22V10 ReportFile : alu4.rpt Program Controls: None. Signal Requests: GROUP DT-OPT ALL GROUP FAST_SLEW ALL Completed Successfully ---------------------------------------------------------------------------- PLD Optimizer Software: DSGNOPT.EXE 11/NOV/97 [v4.02 ] 4 IR x95 OPTIMIZATION OPTIONS (15:44:03) Messages: Information: Process virtual 'c_int_1' ... converted to NODE. Information: Process virtual 'c_int_2' ... converted to NODE. Information: Process virtual 'c_int_3' ... converted to NODE. Information: Optimizing logic using best output polarity for signals: cout y_0 y_1 y_2 y_3 c_int_1 c_int_2 c_int_3 Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Optimizer Software: MINOPT.EXE 11/NOV/97 [v4.02 ] 4 IR x95 LOGIC MINIMIZATION (15:44:03) Messages: Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Optimizer Software: DSGNOPT.EXE 11/NOV/97 [v4.02 ] 4 IR x95 OPTIMIZATION OPTIONS (15:44:03) Messages: Information: Optimizing Banked Preset/Reset requirements. Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: PLA2JED.EXE 11/NOV/97 [v4.02 ] 4 IR x95 DESIGN EQUATIONS (15:44:03) cout = b_3 * func_1 * func_0 * c_int_3 + a_3 * func_1 * func_0 * c_int_3 + a_3 * b_3 * func_1 * func_0 + /func_0 * cout + /func_1 * cout y_0 = func_1 * func_0 * /a_0 * /b_0 * cin + func_0 * a_0 * /b_0 * /cin + func_0 * /a_0 * b_0 * /cin + func_1 * /func_0 * a_0 * /b_0 + func_1 * /func_0 * /a_0 * b_0 + func_0 * a_0 * b_0 * cin + /func_1 * a_0 * b_0 + /func_1 * func_0 * b_0 + /func_1 * func_0 * a_0 y_1 = func_1 * func_0 * /a_1 * /b_1 * c_int_1 + func_0 * a_1 * /b_1 * /c_int_1 + func_0 * /a_1 * b_1 * /c_int_1 + func_1 * /func_0 * a_1 * /b_1 + func_1 * /func_0 * /a_1 * b_1 + func_0 * a_1 * b_1 * c_int_1 + /func_1 * a_1 * b_1 + /func_1 * func_0 * b_1 + /func_1 * func_0 * a_1 y_2 = func_1 * func_0 * /a_2 * /b_2 * c_int_2 + func_0 * a_2 * /b_2 * /c_int_2 + func_0 * /a_2 * b_2 * /c_int_2 + func_1 * /func_0 * a_2 * /b_2 + func_1 * /func_0 * /a_2 * b_2 + func_0 * a_2 * b_2 * c_int_2 + /func_1 * a_2 * b_2 + /func_1 * func_0 * b_2 + /func_1 * func_0 * a_2 y_3 = /a_3 * /b_3 * func_1 * func_0 * c_int_3 + a_3 * /b_3 * func_0 * /c_int_3 + /a_3 * b_3 * func_0 * /c_int_3 + a_3 * /b_3 * func_1 * /func_0 + /a_3 * b_3 * func_1 * /func_0 + a_3 * b_3 * func_0 * c_int_3 + a_3 * b_3 * /func_1 + b_3 * /func_1 * func_0 + a_3 * /func_1 * func_0 c_int_1 = func_1 * func_0 * b_0 * cin + func_1 * func_0 * a_0 * cin + func_1 * func_0 * a_0 * b_0 + /func_0 * c_int_1 + /func_1 * c_int_1 c_int_2 = func_1 * func_0 * b_1 * c_int_1 + func_1 * func_0 * a_1 * c_int_1 + func_1 * func_0 * a_1 * b_1 + /func_0 * c_int_2 + /func_1 * c_int_2 c_int_3 = func_1 * func_0 * b_2 * c_int_2 + func_1 * func_0 * a_2 * c_int_2 + func_1 * func_0 * a_2 * b_2 + /func_0 * c_int_3 + /func_1 * c_int_3 Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: PLA2JED.EXE 11/NOV/97 [v4.02 ] 4 IR x95 DESIGN RULE CHECK (15:44:03) Messages: None. Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: PLA2JED.EXE 11/NOV/97 [v4.02 ] 4 IR x95 DESIGN SIGNAL PLACEMENT (15:44:04) Messages: Information: Checking for duplicate NODE logic. None. C22V10 __________________________________________ not used *| 1| |24|* not used a_3 =| 2| |23|= (c_int_1) a_2 =| 3| |22|= y_3 a_1 =| 4| |21|= y_2 a_0 =| 5| |20|= y_1 b_3 =| 6| |19|= y_0 b_2 =| 7| |18|= cout b_1 =| 8| |17|* not used b_0 =| 9| |16|= (c_int_3) cin =|10| |15|= (c_int_2) not used *|11| |14|= func_1 not used *|12| |13|= func_0 __________________________________________ Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: PLA2JED.EXE 11/NOV/97 [v4.02 ] 4 IR x95 RESOURCE ALLOCATION (15:44:04) Information: Macrocell Utilization. Description Used Max ______________________________________ | Dedicated Inputs | 10 | 11 | | Clock/Inputs | 0 | 1 | | I/O Macrocells | 9 | 10 | ______________________________________ 19 / 22 = 86 % Information: Output Logic Product Term Utilization. Node# Output Signal Name Used Max ________________________________________ | 14 | Used As Input | 0 | 8 | | 15 | c_int_2 | 5 | 10 | | 16 | c_int_3 | 5 | 12 | | 17 | Unused | 0 | 14 | | 18 | cout | 5 | 16 | | 19 | y_0 | 9 | 16 | | 20 | y_1 | 9 | 14 | | 21 | y_2 | 9 | 12 | | 22 | y_3 | 9 | 10 | | 23 | c_int_1 | 5 | 8 | | 25 | Unused | 0 | 1 | ________________________________________ 56 / 121 = 46 % Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: PLA2JED.EXE 11/NOV/97 [v4.02 ] 4 IR x95 JEDEC ASSEMBLE (15:44:04) Messages: Information: Output file 'alu4.jed' created. Summary: Error Count = 0 Warning Count = 0 Completed Successfully at 15:44:04