library ieee; use ieee.std_logic_1164.all; --use work.cypress.all; -- Datapath, part a, for dice game -- two 1-6 counters, adder -- entity dpatha is port ( clk,reset: in std_logic; roll : in std_logic; dicesum: out std_logic_vector(3 downto 0); douta: out std_logic_vector(2 downto 0); doutb: out std_logic_vector(2 downto 0) ); end dpatha; architecture a of dpatha is signal cnta, cntb: std_logic_vector(2 downto 0); signal en_a: std_logic; -- enable for counter A signal sum: std_logic_vector(3 downto 0); signal c1,c2,c3: std_logic; -- carry signals begin douta <= cnta; doutb <= cntb; dicesum <= sum; en_a <= '1' when ((cntb = "110") and (roll = '1')) else '0'; -- State Flip Flops stateff: process (clk,reset) begin if (reset = '1') then cnta <= "001"; -- initialize both counters to '1' cntb <= "001"; elsif (clk'event and clk='1') then if (roll = '1') then case cntb is when "001" => cntb <= "010"; when "010" => cntb <= "011"; when "011" => cntb <= "100"; when "100" => cntb <= "101"; when "101" => cntb <= "110"; when "110" => cntb <= "001"; when others => cntb <= "001"; end case; end if; if (en_a = '1') then case cnta is when "001" => cnta <= "010"; when "010" => cnta <= "011"; when "011" => cnta <= "100"; when "100" => cnta <= "101"; when "101" => cnta <= "110"; when "110" => cnta <= "001"; when others => cnta <= "001"; end case; end if; end if; end process stateff; -- sum equations -- sum = a xor b xor ci -- cout = (a and b) or Ci(a or b) -- bit 0, no carry in sum(0) <= cnta(0) xor cntb(0); c1 <= cnta(0) and cntb(0); -- bit 1, c1 is carry in sum(1) <= cnta(1) xor cntb(1) xor c1; c2 <= (cnta(1) and cntb(1)) or (c1 and (cnta(1) or cntb(1))); -- bit 2, c2 is carry in sum(2) <= cnta(2) xor cntb(2) xor c2; c3 <= (cnta(2) and cntb(2)) or (c2 and (cnta(2) or cntb(2))); -- bit 3 is carry3 since no counter bits sum(3) <= c3; end a;