LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY GND IS
      port (
         Y : out std_logic) ;
END GND;
--
ARCHITECTURE functional OF GND IS
BEGIN
  Y <= '0';
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY MUX2X0 IS
      port (
         A, B, S : in std_logic ;
         Q : out std_logic) ;
END MUX2X0;
--
ARCHITECTURE functional OF MUX2X0 IS
BEGIN
  Q <= (A AND (NOT S)) OR (B AND S) AFTER 5 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY MUX2X1 IS
      port (
         A, B, S : in std_logic ;
         Q : out std_logic) ;
END MUX2X1;
--
ARCHITECTURE functional OF MUX2X1 IS
BEGIN
  Q <= ((NOT A) AND (NOT S)) OR (B AND S) AFTER 5 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY MUX2X2 IS
      port (
         A, B, S : in std_logic ;
         Q : out std_logic) ;
END MUX2X2;
--
ARCHITECTURE functional OF MUX2X2 IS
BEGIN
  Q <= (A AND (NOT S)) OR ((NOT B) AND S) AFTER 5 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY MUX2X3 IS
      port (
         A, B, S : in std_logic ;
         Q : out std_logic) ;
END MUX2X3;
--
ARCHITECTURE functional OF MUX2X3 IS
BEGIN
  Q <= ((NOT A) AND (NOT S)) OR ((NOT B) AND S) AFTER 5 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY MUX4X6 IS
      port (
         A, B, C, D, S0, s1 : in std_logic ;
         Q : out std_logic) ;
END MUX4X6;
--
ARCHITECTURE functional OF MUX4X6 IS
BEGIN
  Q <=       A AFTER 5 NS WHEN s0 = '0' AND s1 = '0' ELSE
       (NOT B) AFTER 5 NS WHEN s0 = '1' AND s1 = '0' ELSE
       (NOT C) AFTER 5 NS WHEN s0 = '0' AND s1 = '1' ELSE
             D AFTER 5 NS WHEN s0 = '1' AND s1 = '1' ELSE
            '0';
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND2I0 IS
     port (
         A, B : in std_logic ;
         Q : out std_logic) ;
END AND2I0;
--
ARCHITECTURE functional OF AND2I0 IS
BEGIN
  Q <= A AND B AFTER 3 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND2I1 IS
     port (
         A, B : in std_logic ;
         Q : out std_logic) ;
END AND2I1;
--
ARCHITECTURE functional OF AND2I1 IS
BEGIN
  Q <= A AND (NOT B) AFTER 3 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND2I2 IS
     port (
         A, B : in std_logic ;
         Q : out std_logic) ;
END AND2I2;
--
ARCHITECTURE functional OF AND2I2 IS
BEGIN
  Q <= (NOT A) AND (NOT B) AFTER 3 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND3I0 IS
     port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
END AND3I0;
--
ARCHITECTURE functional OF AND3I0 IS
BEGIN
  Q <= A AND B AND C AFTER 5 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND3I1 IS
     port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
END AND3I1;
--
ARCHITECTURE functional OF AND3I1 IS
BEGIN
  Q <= A AND B AND (NOT C) AFTER 5 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND3I2 IS
     port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
END AND3I2;
--
ARCHITECTURE functional OF AND3I2 IS
BEGIN
  Q <= A AND (NOT B) AND (NOT C) AFTER 5 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND3I3 IS
     port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
END AND3I3;
--
ARCHITECTURE functional OF AND3I3 IS
BEGIN
  Q <= (NOT A) AND (NOT B) AND (NOT C) AFTER 5 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND4I0 IS
     port (
         A, B, C, D : in std_logic ;
         Q : out std_logic) ;
END AND4I0;
--
ARCHITECTURE functional OF AND4I0 IS
BEGIN
  Q <= A AND B AND C AND D AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND4I1 IS
     port (
         A, B, C, D : in std_logic ;
         Q : out std_logic) ;
END AND4I1;
--
ARCHITECTURE functional OF AND4I1 IS
BEGIN
  Q <= A AND B AND C AND (NOT D) AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND4I2 IS
     port (
         A, B, C, D : in std_logic ;
         Q : out std_logic) ;
END AND4I2;
--
ARCHITECTURE functional OF AND4I2 IS
BEGIN
  Q <= A AND B AND (NOT C) AND (NOT D) AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND4I3 IS
     port (
         A, B, C, D : in std_logic ;
         Q : out std_logic) ;
END AND4I3;
--
ARCHITECTURE functional OF AND4I3 IS
BEGIN
  Q <= A AND (NOT B) AND (NOT C) AND (NOT D) AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND4I4 IS
     port (
         A, B, C, D : in std_logic ;
         Q : out std_logic) ;
END AND4I4;
--
ARCHITECTURE functional OF AND4I4 IS
BEGIN
  Q <= (NOT A) AND (NOT B) AND (NOT C) AND (NOT D) AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND5I0 IS
     port (
         A, B, C, D, E : in std_logic ;
         Q : out std_logic) ;
END AND5I0;
--
ARCHITECTURE functional OF AND5I0 IS
BEGIN
  Q <= A AND B AND C AND D AND E AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND5I1 IS
     port (
         A, B, C, D, E : in std_logic ;
         Q : out std_logic) ;
END AND5I1;
--
ARCHITECTURE functional OF AND5I1 IS
BEGIN
  Q <= A AND B AND C AND D AND (NOT E) AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND5I2 IS
     port (
         A, B, C, D, E : in std_logic ;
         Q : out std_logic) ;
END AND5I2;
--
ARCHITECTURE functional OF AND5I2 IS
BEGIN
  Q <= A AND B AND C AND (NOT D) AND (NOT E) AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND5I3 IS
     port (
         A, B, C, D, E : in std_logic ;
         Q : out std_logic) ;
END AND5I3;
--
ARCHITECTURE functional OF AND5I3 IS
BEGIN
  Q <= A AND B AND (NOT C) AND (NOT D) AND (NOT E) AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND5I4 IS
     port (
         A, B, C, D, E : in std_logic ;
         Q : out std_logic) ;
END AND5I4;
--
ARCHITECTURE functional OF AND5I4 IS
BEGIN
  Q <= A AND (NOT B) AND (NOT C) AND (NOT D) AND (NOT E) AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND5I5 IS
     port (
         A, B, C, D, E : in std_logic ;
         Q : out std_logic) ;
END AND5I5;
--
ARCHITECTURE functional OF AND5I5 IS
BEGIN
  Q <= (NOT A) AND (NOT B) AND (NOT C) AND (NOT D) AND (NOT E) AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND6I0 IS
     port (
         A, B, C, D, E, F : in std_logic ;
         Q : out std_logic) ;
END AND6I0;
--
ARCHITECTURE functional OF AND6I0 IS
BEGIN
  Q <= A AND B AND C AND D AND E AND F AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND6I1 IS
     port (
         A, B, C, D, E, F : in std_logic ;
         Q : out std_logic) ;
END AND6I1;
--
ARCHITECTURE functional OF AND6I1 IS
BEGIN
  Q <= A AND B AND C AND D AND E AND (NOT F) AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND6I2 IS
     port (
         A, B, C, D, E, F : in std_logic ;
         Q : out std_logic) ;
END AND6I2;
--
ARCHITECTURE functional OF AND6I2 IS
BEGIN
  Q <= A AND B AND C AND D AND (NOT E) AND (NOT F) AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND6I3 IS
     port (
         A, B, C, D, E, F : in std_logic ;
         Q : out std_logic) ;
END AND6I3;
--
ARCHITECTURE functional OF AND6I3 IS
BEGIN
  Q <= A AND B AND C AND (NOT D) AND (NOT E) AND (NOT F) AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND6I4 IS
     port (
         A, B, C, D, E, F : in std_logic ;
         Q : out std_logic) ;
END AND6I4;
--
ARCHITECTURE functional OF AND6I4 IS
BEGIN
  Q <= A AND B AND (NOT C) AND (NOT D) AND (NOT E) AND (NOT F) AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND6I5 IS
     port (
         A, B, C, D, E, F : in std_logic ;
         Q : out std_logic) ;
END AND6I5;
--
ARCHITECTURE functional OF AND6I5 IS
BEGIN
  Q <= A AND (NOT B) AND (NOT C) AND (NOT D) AND (NOT E) AND (NOT F) AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY AND6I6 IS
     port (
         A, B, C, D, E, F : in std_logic ;
         Q : out std_logic) ;
END AND6I6;
--
ARCHITECTURE functional OF AND6I6 IS
BEGIN
  Q <= (NOT A) AND (NOT B) AND (NOT C) AND (NOT D) AND (NOT E) AND (NOT F) AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY OR2I0 IS
     port (
         A, B : in std_logic ;
         Q : out std_logic) ;
END OR2I0;
--
ARCHITECTURE functional OF OR2I0 IS
BEGIN
  Q <= A OR B AFTER 3 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY OR2I1 IS
     port (
         A, B : in std_logic ;
         Q : out std_logic) ;
END OR2I1;
--
ARCHITECTURE functional OF OR2I1 IS
BEGIN
  Q <= A OR (NOT B) AFTER 3 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY OR2I2 IS
     port (
         A, B : in std_logic ;
         Q : out std_logic) ;
END OR2I2;
--
ARCHITECTURE functional OF OR2I2 IS
BEGIN
  Q <= (NOT A) OR (NOT B) AFTER 3 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY OR3I0 IS
     port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
END OR3I0;
--
ARCHITECTURE functional OF OR3I0 IS
BEGIN
  Q <= A OR B OR C AFTER 3 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY OR3I1 IS
     port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
END OR3I1;
--
ARCHITECTURE functional OF OR3I1 IS
BEGIN
  Q <= A OR B OR (NOT C) AFTER 3 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY OR3I2 IS
     port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
END OR3I2;
--
ARCHITECTURE functional OF OR3I2 IS
BEGIN
  Q <= A OR (NOT B) OR (NOT C) AFTER 3 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY OR3I3 IS
     port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
END OR3I3;
--
ARCHITECTURE functional OF OR3I3 IS
BEGIN
  Q <= (NOT A) OR (NOT B) OR (NOT C) AFTER 3 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY XOR3I0 IS
     port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
END XOR3I0;
--
ARCHITECTURE functional OF XOR3I0 IS
BEGIN
  Q <= (A XOR B) XOR C AFTER 5 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY XNOR2I0 IS
     port (
         A, B : in std_logic ;
         Q : out std_logic) ;
END XNOR2I0;
--
ARCHITECTURE functional OF XNOR2I0 IS
BEGIN
  Q <= ( NOT A) XOR B AFTER 3 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY XNOR3I0 IS
     port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
END XNOR3I0;
--
ARCHITECTURE functional OF XNOR3I0 IS
BEGIN
  Q <= ( NOT A) XOR B XOR C AFTER 3 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY MAJ3I0 IS
     port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
END MAJ3I0;
--
ARCHITECTURE functional OF MAJ3I0 IS
BEGIN
  Q <= (A AND B) OR (A AND C) OR (B AND C) AFTER 6 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY INV IS
      port (
         A : in std_logic ;
         Q : out std_logic) ;
END INV;
--
ARCHITECTURE functional OF INV IS
BEGIN
  Q <= NOT A AFTER 3 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY BUFF IS
      port (
         A : in std_logic ;
         Q : out std_logic) ;
END BUFF;
--
ARCHITECTURE functional OF BUFF IS
BEGIN
  Q <= A AFTER 4 NS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY DFFPC IS
      port (
         CLK, CLR, D, PRE : in std_logic ;
         Q : out std_logic := '1') ;
END DFFPC;
--
ARCHITECTURE functional OF DFFPC IS
BEGIN
  PROCESS (CLK, CLR, PRE)
  BEGIN
    IF CLR = '1' THEN
      Q <= '0' AFTER 3 NS;
    ELSIF PRE = '1' THEN
      Q <= '1' AFTER 3 NS;
    ELSIF (CLK = '1' AND CLK'EVENT) THEN
      Q <= D AFTER 4 NS;
    END IF;
  END PROCESS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY DFFC IS
      port (
         CLK, CLR, D : in std_logic ;
         Q : out std_logic := '1') ;
END DFFC;
--
ARCHITECTURE functional OF DFFC IS
BEGIN
  PROCESS (CLK, CLR)
  BEGIN
    IF CLR = '1' THEN
      Q <= '0' AFTER 3 NS;
    ELSIF (CLK = '1' AND CLK'EVENT) THEN
      Q <= D AFTER 4 NS;
    END IF;
  END PROCESS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY DFF IS
      port (
         CLK, D : in std_logic ;
         Q : out std_logic := '0') ;
END DFF;
--
ARCHITECTURE functional OF DFF IS
BEGIN
  PROCESS (CLK)
  BEGIN
    IF (CLK = '1' AND CLK'EVENT) THEN
      Q <= D AFTER 4 NS;
    END IF;
  END PROCESS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
ENTITY DLA IS
      port (
         D, G : in std_logic ;
         Q : out std_logic := '0') ;
END DLA;
--
ARCHITECTURE functional OF DLA IS
BEGIN
  PROCESS (G, D)
  BEGIN
    IF (G = '1') THEN
      Q <= D AFTER 3 NS;
    END IF;
  END PROCESS;
END functional;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
PACKAGE Cypress_pASIC IS
   component GND
      port (
         Y : out std_logic) ;
   end component ;
   component MUX2X0
      port (
         A, B, S : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component MUX2X1
      port (
         A, B, S : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component MUX2X2
      port (
         A, B, S : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component MUX2X3
      port (
         A, B, S : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component MUX4X6
      port (
         A, B, C, D, S0, S1 : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND2I0
      port (
         A, B : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND2I1
      port (
         A, B : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND2I2
      port (
         A, B : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND3I0
      port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND3I1
      port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND3I2
      port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND3I3
      port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND4I0
      port (
         A, B, C, D : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND4I1
      port (
         A, B, C, D : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND4I2
      port (
         A, B, C, D : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND4I3
      port (
         A, B, C, D : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND4I4
      port (
         A, B, C, D : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND5I0
      port (
         A, B, C, D, E : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND5I1
      port (
         A, B, C, D, E : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND5I2
      port (
         A, B, C, D, E : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND5I3
      port (
         A, B, C, D, E : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND5I4
      port (
         A, B, C, D, E : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND5I5
      port (
         A, B, C, D, E : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND6I0
      port (
         A, B, C, D, E, F : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND6I1
      port (
         A, B, C, D, E, F : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND6I2
      port (
         A, B, C, D, E, F : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND6I3
      port (
         A, B, C, D, E, F : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND6I4
      port (
         A, B, C, D, E, F : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND6I5
      port (
         A, B, C, D, E, F : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND6I6
      port (
         A, B, C, D, E, F : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component OR2I0
      port (
         A, B : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component OR2I1
      port (
         A, B : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component OR2I2
      port (
         A, B : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component OR3I0
      port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component OR3I1
      port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component OR3I2
      port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component OR3I3
      port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component XOR2I0
      port (
         A, B : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component XOR3I0
      port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component XNOR2I0
      port (
         A, B : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component XNOR3I0
      port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component MAJ3I0
      port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component INV
      port (
         A : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component BUFF
      port (
         A : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component DFFPC
      port (
         CLK, CLR, D, PRE : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component DFFC
      port (
         CLK, CLR, D : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component DFF
      port (
         CLK, D : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component DLA
      port (
         D, G : in std_logic ;
         Q : out std_logic) ;
   end component ;
END Cypress_pASIC;