GL85erm DESCRIPTION. (erm1.u-strasbg.fr) Attest Sofware, Inc. has set up on december 1993 an anonymous directory on Internet to make behavioral level model of a circuit called gl85. The file i8085.vhd was written in VHDL but was not compilable, and then not simulable, on the V_System/Windows release 3.3. Furthermore, some functions used in the model were not available in current librairies. So, the initial behavioral model has been corrected and the new version proposed in the file i8085erm.vhd is compilable and simulable under V_System/Windows release 3.3, provided you have copied the file convers.vhd, which contains the package of the functions required in library. The description of functions and corrections made can be found further in this text. Attest Software, Inc had also given a file named i8085.vec in order to simulate their model. Except some very little changes, the file i8085_2.vec has the same function and can be used with the file read_vec.vhd. Finally, if you want to simulate the behavorial model of gl85 with its associated design verification vectors, use the file simgl85.vhd. The model gl85_erm has been simulated and its results have been checked. However, the corrections made were strictly in an attempt of compilation and simulation and absolutly not in order to improve the model, or its description. FILES README TXT This file I8085ERM VHD 123,463 Behavioral model CONVERS VHD 3,307 Utilities package SIMGL85 VHD 2,191 Test Bench I8085_2 VEC 22,778 Input vectors READ_VEC VHD 1,883 Reader of *.vec Description of corrections made on i8085.vhd * Using of the package ieee.std_logic_1164, in order to replace the type bit by std_ulogic. This change was necessary because some signals has to be resolved (type std_logic). -- hlda : line 28. -- wr_mod, holdff, inteff : line 42. -- hltaff : line 45. -- trapff : line 68. -- rst75ff : line 70. -- cc6 : line 71. All these resolved signals have been initialised to 'Z', i.e. high impedance state. * All bit values were assigned this way : bit <= value . As this was not accepted by the compilator, it has been changed to : bit <= ' value '. For vectors, two forms are possible : bit_vector <= (' value1 ',' value2' ,.... ) or bit_vector <= "value1value2....." . * The expression up_edge(clock) has been replaced by : clock='1' and not (clock'stable). ( Lines 123, 160, 1777, 1784, 1899) In the same way, down_edge(clock) has become clock='0' and not (clock'stable). ( Lines 1687, 1915) * The instruction case must be entirely defined, so in allmost all uses the line : " when others => null " has been added at the end of the case definition. * The type logic_state, added in the package conversion, is an integer between 0 and 1 but the compilator does not allow the assignation bit <= logic_state. So some signals which type was logic_state have been changed into bit, i.e. std_ulogic or std_logic if the signal must be resolved. -- wr_mod, holdff, inteff : line 42. -- resetoutff : line 43. -- intrff : line 81. * In order to use correctly the logical functions or, and, ...and so on, the compilator need parenthesis between groups of two variables or signals . Example : "a and b and c" is not compilable, and the good way to write it is "(a and b) and c" ( Lines 1654, 1666, 1676, 1699, 1705, 1712, 1716, 1728, 1742) * The only modification made without being absolutly necessary concerns the use of the instruction loop instead of 7 lines repeated. ( Lines 196, 201, 206) description of package conversion * It contains functions that convert bit vectors to integers and inversely integers to bit vectors. The function bit2int and the procedure int2bit have been overloaded in order to be used with bit vectors or with only a bit. * Unfortunately, it is impossible to overload functions or procedures with the class of their inputs. So we create a function called bit2int_sig and a procedure called int2bit_sig . They have the same utility than bit2int and int2bit but their inputs are signals and not variables. * Procedures inc and dec (and their equivalent for signals : inc_sig and dec_sig) are used to increment or decrement bit vectors. * The type logic_state, not often used in our model, is defined as an integer which value is 0 or 1. Celine POLOCE 08/1994 and !!!! My VHDL is better than my English (I hope)!!! |^^^^^^| __________________________________ | | / Dr Yannick HERVE \ | | | MACAO Team of ERM/PHASE | | (o)(o) | ENSPS, Parc d'Innovations | @ _) | 67400 ILLKIRCH, FRANCE | | ,___| ,,| Phone:(33)88655094 Fax(33)88655249 | | / ..'' | Email: yann@erm2.u-strasbg.fr | /____\ \__________________________________/ MACAO: Methodes Avancees pour la CAO (in english AMCAD: Advanced Methods for CAD)