--**********************************************************************
--  This file contains all the VHDL files for the Floating Point Adder
--  example concatenated together for download convenience.  Note they
--  have also been put in analysis order for convenience; but not analyzed
--  to verify the results!
--**********************************************************************

--**********************************************************************
-- typeconv.vhd
--------  VHDL Repository Prolog ------------
--
-- Unit name    : Floating Point Adder Type Conversion Support Package
-- Version      : 1.0
-- Author       : Jo DeGroat
--              : Air Force Institute of Technology
-- DDN Address  : jdegroat@blackbird.afit.af.mil
-- Copyright    : (c) Air Force Institute of Technology
-- Date created : August 1988
-- Release date : June 15,1989
-- Last update  : June 15,1989
-- VHDL Version : IEEE Std 1076
-- Machine/System Analyzed/Simulated on: Simulated on VAX 11/785
--                using Intermetrics VHDL system, version 1.5b under VMS
---------------------------------------------------------------
-- Keywords     : Floating Point, Adder
-- Abstract     : This VHDL file is the fpa type conversion package.
--                It contains routines for the support of the fpa adder.
--                The procedures and functions contained inplement type
--                conversion functions bit to integer and routines to
--                convert ieee std754 floating point (double precision)
--                to notations for printing.
------------------ Revision history ---------------------------
-- DATE         VERSION AUTHOR       HISTORY
-- 15 June 1989   1.0   Jo DeGroat   Initial Release
------------------ Distribution and Copyright -----------------
-- This prologue must be included in all copies of this VHDL code.
-- This description is copyright by the author.
-- This description is released to the VHDL community.
-- Restrictions on use or distribution:  NONE
------------------ Disclaimer ---------------------------------
-- This VHDL description code and its documentation are provided
-- "AS IS" and without any expressed or implied warranties
-- whatsoever.  No warranties as to performance, merchantability,
-- or fitness for a particular purpose exist.
--
-- Because of the diversity of conditions under which this code
-- may be used, no warranty of fitness for a particular purpose
-- is offered.  The user is advised to evaluate the code
-- thoroughly before relying on it.  The user must assume the
-- entire risk and liability of using this code.
--
-- In no event shall any person or organization of people be
-- held responsible for any direct, indirect, consequential
-- or inconsequential damages or lost profits.
-------------------END-PROLOG--------------------------------
package type_conversion is

   function bit2int (bitval : in BIT_VECTOR) return INTEGER;
   function bit2int (bitval : in BIT       ) return INTEGER;
   function mantissaval (intbit : in BIT; fract : in BIT_VECTOR) return REAL;
   procedure ieee2real (variable bitrep : in BIT_VECTOR;
                        variable comment : out STRING;
                        variable realval : out REAL);
   procedure ieee_exp_man (variable bitrep : in BIT_VECTOR;
                           variable expval : out INTEGER;
                           variable manval : out REAL);

end type_conversion;

package body type_conversion is
-- -------------------------------------------
--
-- type conversion from BIT_VECTOR to INTEGER
--
   function bit2int (bitval : in BIT_VECTOR) return INTEGER is

      variable weight,cur_value : INTEGER;
      variable msb,lsb : INTEGER;

   begin
      weight  := 1;
      cur_value := 0;
      msb := bitval'left;
      lsb := bitval'right;
      for I in lsb to msb loop
         if (bitval(I) = '1') then cur_value := cur_value + weight; end if;
         weight  := weight + weight;
      end loop;
      return cur_value;
   end bit2int;
--
-- bit version of function
--
   function bit2int (bitval : in BIT       ) return INTEGER is
      variable intval : INTEGER;
   begin
      if (bitval = '1') then intval := 1; else intval :=0; end if;
      return intval;
   end bit2int;
--
-- -------------------------------------------------
--
   function mantissaval (intbit : in BIT; fract : in BIT_VECTOR) return REAL is
      variable weight,cur_value : REAL;
      variable msb,lsb : INTEGER;
   begin
      weight := 0.5; cur_value := 0.0;
      msb := fract'left; lsb := fract'right;
      for I in msb downto lsb loop
         if (fract(I) = '1') then cur_value := cur_value + weight; end if;
         weight := weight / 2.0;
      end loop;
      if (intbit = '1') then cur_value := cur_value + 1.0; end if;
      return cur_value;
   end mantissaval;

   procedure ieee2real (variable bitrep : in BIT_VECTOR;
                        variable comment : out STRING;
                        variable  realval : out REAL) is
      variable sign : BIT;
      variable signchar : CHARACTER;
      variable exp  : BIT_VECTOR (10 downto 0);
      variable man  : BIT_VECTOR (51 downto 0);
      variable tempmanval : REAL;
      variable tempexpval : INTEGER;
      constant expall0 : BIT_VECTOR (10 downto 0):= "00000000000";
      constant expall1 : BIT_VECTOR (10 downto 0):= "11111111111";
      constant maxexp  : BIT_VECTOR (10 downto 0):= "10001111101";
      constant manall0 : BIT_VECTOR (51 downto 0):= X"0_0000_0000_0000";
   begin
      sign := bitrep (63);
      exp  := bitrep (62 downto 52);
      man  := bitrep (51 downto 0);
      if (sign = '0') then signchar := '+';
                      else signchar := '-'; 
      end if;
      if ((exp = expall1) and (man /= manall0)) then
         comment := signchar & "Nan    "; realval := 0.0; return;
      elsif ((exp = expall1) and (man = manall0)) then
         comment := signchar & "inif   "; realval := 0.0; return;
      elsif ((exp = expall0) and (man = manall0)) then
         comment := signchar & "zero   "; realval := 0.0; return;
      elsif (exp > maxexp) then
         comment := signchar & "range  "; realval := 0.0; return;
      elsif ((exp = expall0) and (man /= manall0)) then
         comment := signchar & "denorm ";
         tempmanval := mantissaval ('0',man);
         tempexpval := -1022;
         if (sign = '0') then realval := tempmanval * (2.0 ** tempexpval);
                         else realval := -tempmanval * (2.0 ** tempexpval);
         end if;
         return;
      else
         comment := signchar & "value  ";
         tempmanval := mantissaval ('1',man);
         tempexpval := bit2int (exp) - 1023;
         if (sign = '0') then realval := tempmanval * (2.0 ** tempexpval);
                         else realval := -tempmanval * (2.0 ** tempexpval);
         end if;
         return;
      end if;
   end ieee2real;

   procedure ieee_exp_man (variable bitrep : in BIT_VECTOR;
                           variable expval : out INTEGER;
                           variable manval : out REAL) is
      variable exp  : BIT_VECTOR (10 downto 0);
      variable man  : BIT_VECTOR (51 downto 0);
      constant expall0 : BIT_VECTOR (10 downto 0):= "00000000000";
      constant manall0 : BIT_VECTOR (51 downto 0):= X"0_0000_0000_0000";
   begin
      exp  := bitrep (62 downto 52);
      man  := bitrep (51 downto 0);
      if (exp = expall0 and man /= manall0)
                         then expval := bit2int (exp) - 1022;
                         else expval := bit2int (exp) - 1023;
      end if;
      if (exp = expall0) then  manval := mantissaval ('0',man);
                         else  manval := mantissaval ('1',man);
      end if;
      return;
   end ieee_exp_man;

end type_conversion;
--**********************************************************************

--**********************************************************************
-- fparesc.vhd
--------  VHDL Repository Prolog ------------
--
-- Unit name    : Floating Point Adder Resources Package
-- Version      : 1.0
-- Author       : Jo DeGroat
--              : Air Force Institute of Technology
-- DDN Address  : jdegroat@blackbird.afit.af.mil
-- Copyright    : (c) Air Force Institute of Technology
-- Date created : August 1988
-- Release date : June 15,1989
-- Last update  : June 15,1989
-- VHDL Version : IEEE Std 1076
-- Machine/System Analyzed/Simulated on: Simulated on VAX 11/785
--                using Intermetrics VHDL system, version 1.5b under VMS
---------------------------------------------------------------
-- Keywords     : Floating Point, Adder
-- Abstract     : This VHDL file is the fpa resources package.
--                It contains routines for the support of the fpa adder.
--                The procedures and functions contained inplement hardware
--                macrocell units for the fpa such as adders, shifters, etc.
------------------ Revision history ---------------------------
-- DATE         VERSION AUTHOR       HISTORY
-- 15 June 1989   1.0   Jo DeGroat   Initial Release
------------------ Distribution and Copyright -----------------
-- This prologue must be included in all copies of this VHDL code.
-- This description is copyright by the author.
-- This description is released to the VHDL community.
-- Restrictions on use or distribution:  NONE
------------------ Disclaimer ---------------------------------
-- This VHDL description code and its documentation are provided
-- "AS IS" and without any expressed or implied warranties
-- whatsoever.  No warranties as to performance, merchantability,
-- or fitness for a particular purpose exist.
--
-- Because of the diversity of conditions under which this code
-- may be used, no warranty of fitness for a particular purpose
-- is offered.  The user is advised to evaluate the code
-- thoroughly before relying on it.  The user must assume the
-- entire risk and liability of using this code.
--
-- In no event shall any person or organization of people be
-- held responsible for any direct, indirect, consequential
-- or inconsequential damages or lost profits.
-------------------END-PROLOG--------------------------------
library STD,WORK;
use STD.TEXTIO.all;
use WORK.type_conversion.all;
package fparesc is

   procedure bitadd(variable A,B,Cin : in BIT; variable S,Cout : out BIT);

   function expdist(A,B : in BIT_VECTOR) return BIT_VECTOR;

   function shift (dist : in BIT_VECTOR; bitstring : in BIT_VECTOR)
                   return BIT_VECTOR;

   function csadd(addend,augend:in BIT_VECTOR; C_in0:in BIT) return BIT_VECTOR;

   function leadingone(bvin : in BIT_VECTOR) return BIT_VECTOR;

   function increment6(bvin : in BIT_VECTOR) return BIT_VECTOR;

   function expincr (bvin : in BIT_VECTOR) return BIT_VECTOR;

   function lgexpadder(addend,augend:in BIT_VECTOR) return BIT_VECTOR;

   function leftshift(bvin:in BIT_VECTOR; dist:in BIT_VECTOR) return BIT_VECTOR;

   function manincr (bvin : in BIT_VECTOR) return BIT_VECTOR;

end fparesc;

package body fparesc is

   procedure bitadd(variable A,B,Cin : in BIT; variable S,Cout : out BIT) is
   begin
      S := A xor B xor Cin;
      Cout := (A and B) or (A and Cin) or (B and Cin);
   end bitadd;

   function expdist(A,B : in BIT_VECTOR) return BIT_VECTOR is
      variable ValA,ValB,Diff : BIT_VECTOR(10 downto 0);
      variable Cin,Cout : Bit;
      variable I : integer;
      variable shift_dist :BIT_VECTOR(5 downto 0); 
   begin
      Cout := '1';
      if (A>=B) then ValA := A;     ValB := not B;
                else ValA := not A; ValB := B;
      end if;
      for I in 0 to 10 loop
         Cin := Cout;
         bitadd (ValA(I),ValB(I),Cin,Diff(I),Cout);
      end loop;
      if (Diff(10 downto 6) = "00000") then shift_dist := diff (5 downto 0);
                                       else shift_dist := "111111";
      end if;
      return shift_dist;
   end expdist;

   function shift (dist : in BIT_VECTOR; bitstring : in BIT_VECTOR)
                   return BIT_VECTOR is
      variable distval,I,J : INTEGER;
      variable targetstring : BIT_VECTOR (56 downto 0);
   begin
      for I in 0 to 56 loop targetstring(I):='0'; end loop;
      distval := bit2int(dist);
      I := 56-distval ; J := 52;
      while (I >= 0) and (J >= 0) loop
         targetstring(I):= bitstring(J);
         I := I - 1; J := J - 1;
      end loop;
      return targetstring;
   end shift;

   function csadd(addend,augend:in BIT_VECTOR; C_in0:in BIT) return BIT_VECTOR
   is
      variable SUM : BIT_VECTOR(58 downto 0);
      variable addendin,augendin : BIT_VECTOR(57 downto 0);
      variable Cin,Cout : BIT;
   begin
      Cin := C_in0;
      addendin := addend; augendin := augend;
      for I in 0 to 57 loop
         bitadd (addendin(I),augendin(I),Cin,SUM(I),Cout);
         Cin := Cout;
      end loop;
      SUM(58) := Cout;
      return SUM;
   end csadd;

   function increment6(bvin : in BIT_VECTOR) return BIT_VECTOR is
      variable incrval : BIT_VECTOR (5 downto 0);
      variable carry   : BIT;
   begin
      carry := '1';
      for I in 0 to 5 loop
         incrval(I) := carry xor bvin(I);
         carry      := carry and bvin(I);
      end loop;
      return incrval;
   end increment6;

   function leadingone(bvin : in BIT_VECTOR) return BIT_VECTOR is
      variable J : INTEGER;
      variable position : BIT_VECTOR (5 downto 0);
   begin
      position := "000001";
      J := 55;
      while ((J > 0) and (bvin(J) = '0')) loop
         position := increment6 (position);
         J := J - 1;
      end loop;
      return position;
   end leadingone;

   function expincr (bvin : in BIT_VECTOR) return BIT_VECTOR is
      variable incrval : BIT_VECTOR (10 downto 0);
      variable carry   : BIT;
   begin
      carry := '1';
      for I in 0 to 10 loop
         incrval(I) := carry xor bvin(I);
         carry      := carry and bvin(I);
      end loop;
      return incrval;
   end expincr;

   function lgexpadder(addend,augend:in BIT_VECTOR) return BIT_VECTOR is
      variable SUM : BIT_VECTOR(11 downto 0);
      variable addendin,augendin : BIT_VECTOR(11 downto 0);
      variable Cin,Cout : BIT;
   begin
      Cin := '1';
      addendin := addend; augendin := augend;
      for I in 0 to 11 loop
         bitadd (addendin(I),augendin(I),Cin,SUM(I),Cout);
         Cin := Cout;
      end loop;
      return SUM;
   end lgexpadder;

   function leftshift(bvin:in BIT_VECTOR; dist:in BIT_VECTOR) return BIT_VECTOR
   is
      variable distval,I,J : INTEGER;
      variable targetstring : BIT_VECTOR (57 downto 0);
   begin
      for I in 0 to 57 loop targetstring(I):='0'; end loop;
      distval := bit2int(dist);
      I := 57; J := 57-distval;
      while (I >= 0) and (J >= 0) loop
         targetstring(I):= bvin(J);
         I := I - 1; J := J - 1;
      end loop;
      return targetstring;
   end leftshift;

   function manincr (bvin : in BIT_VECTOR) return BIT_VECTOR is
      variable incrval : BIT_VECTOR (52 downto 0);
      variable carry   : BIT;
   begin
      carry := '1';
      for I in 0 to 52 loop
         incrval(I) := carry xor bvin(I);
         carry      := carry and bvin(I);
      end loop;
      return incrval;
   end manincr;

end fparesc;
--**********************************************************************

--**********************************************************************
-- print.vhd
--------  VHDL Repository Prolog ------------
--
-- Unit name    : Floating Point Adder Textio Routine Package
-- Version      : 1.0
-- Author       : Jo DeGroat
--              : Air Force Institute of Technology
-- DDN Address  : jdegroat@blackbird.afit.af.mil
-- Copyright    : (c) Air Force Institute of Technology
-- Date created : August 1988
-- Release date : June 15,1989
-- Last update  : June 15,1989
-- VHDL Version : IEEE Std 1076
-- Machine/System Analyzed/Simulated on: Simulated on VAX 11/785
--                using Intermetrics VHDL system, version 1.5b under VMS
---------------------------------------------------------------
-- Keywords     : Floating Point, Adder
-- Abstract     : This VHDL file is the fpa textio routines package.
--                It contains routines for the support of the fpa adder.
--                The procedures implemented here are invoked as concurrent
--                procedure calls or sequential procedure calls in the fpa
--                adder.  They write to a resutls file that can be examined
--                to see the status and flow of data through the adder.
------------------ Revision history ---------------------------
-- DATE         VERSION AUTHOR       HISTORY
-- 15 June 1989   1.0   Jo DeGroat   Initial Release
------------------ Distribution and Copyright -----------------
-- This prologue must be included in all copies of this VHDL code.
-- This description is copyright by the author.
-- This description is released to the VHDL community.
-- Restrictions on use or distribution:  NONE
------------------ Disclaimer ---------------------------------
-- This VHDL description code and its documentation are provided
-- "AS IS" and without any expressed or implied warranties
-- whatsoever.  No warranties as to performance, merchantability,
-- or fitness for a particular purpose exist.
--
-- Because of the diversity of conditions under which this code
-- may be used, no warranty of fitness for a particular purpose
-- is offered.  The user is advised to evaluate the code
-- thoroughly before relying on it.  The user must assume the
-- entire risk and liability of using this code.
--
-- In no event shall any person or organization of people be
-- held responsible for any direct, indirect, consequential
-- or inconsequential damages or lost profits.
-------------------END-PROLOG--------------------------------
library STD,WORK;
use STD.TEXTIO.all;
use WORK.type_conversion.all;
use WORK.fparesc.all;

package print is

   constant space6 : STRING := "      ";
   constant space8 : STRING := "        ";
   constant space18 : STRING := "                  ";
   file resfile : TEXT is out "resfile";
   procedure write_abbus(signal A_Bus,B_Bus: in BIT_VECTOR);
   procedure write_abinp(signal aval,bval: in BIT_VECTOR);
   procedure write_expsig(signal gt,eq,lt,a0,a1,b0,b1: in BIT;
                          signal dist,lgr: in BIT_VECTOR);
   procedure write_mansig(signal gt,eq,lt,a0,b0: in BIT);
   procedure write_xbar(signal swap: in BIT; signal xbarr,xbarl: in BIT_VECTOR);
   procedure write_inmux(signal rnan,lzero: in BIT;
                         signal rout,lout: in BIT_VECTOR);
   procedure write_shf(signal dist:in BIT_VECTOR;signal shfout:in BIT_VECTOR);
   procedure write_twoscompout(signal twoscomp : in BIT;
                               signal ladderin,radderin : in BIT_VECTOR);
   procedure write_adderout(signal addersum : in BIT_VECTOR);
   procedure write_adderoutsig(signal dec1,dec2,fract0 : in BIT;
                               signal leading1pos : in BIT_VECTOR);
   procedure write_exp_choices(signal plus,larger : in BIT_VECTOR;
                               signal adjusted    : in BIT_VECTOR);
   procedure write_normalized(signal sign : BIT;
                              signal exponent : BIT_VECTOR;
                              signal mantissa : BIT_VECTOR);
   procedure write_rounded   (signal sign : BIT;
                              signal exponent : BIT_VECTOR;
                              signal mantissa : BIT_VECTOR);
   procedure write_final   (signal sign : BIT;
                            signal exponent : BIT_VECTOR;
                            signal mantissa : BIT_VECTOR;
                            signal flags : BIT_VECTOR);

end print;

package body print is

   procedure write_abbus(signal A_Bus,B_Bus: in BIT_VECTOR) is
      variable ptr : LINE;
      variable noteout : STRING (1 to 7);
      variable valout  : BIT_VECTOR (63 downto 0);
   begin
      write(ptr,' '); writeline(resfile,ptr);
      write(ptr,NOW,FIELD=>6);
      noteout := " ABUS= "; write(ptr,noteout);
      valout := A_Bus;      write(ptr,valout(63));
      write(ptr,' '); write(ptr,valout(62 downto 52));
      write(ptr,' '); write(ptr,valout(51 downto 0 ));
      writeline(resfile,ptr);
      write(ptr,space6);
      noteout := " BBUS= "; write(ptr,noteout);
      valout := B_Bus;      write(ptr,valout(63));
      write(ptr,' '); write(ptr,valout(62 downto 52));
      write(ptr,' '); write(ptr,valout(51 downto 0 ));
      writeline(resfile,ptr);
   end write_abbus;

   procedure write_abinp(signal aval,bval: in BIT_VECTOR) is
      variable ptr : LINE;
      variable noteout : STRING (1 to 7);
      variable note8 : STRING (1 to 8);
      variable valout  : BIT_VECTOR (63 downto 0);
      variable realval,manval : REAL;
      variable expval : INTEGER;
   begin
      write(ptr,NOW,FIELD=>6);
      noteout := " A inp "; write(ptr,noteout);
      valout := aval;          write(ptr,valout(63));
      write(ptr,' '); write(ptr,valout(62 downto 52));
      write(ptr,' '); write(ptr,valout(51 downto 0 ));
      writeline(resfile,ptr);
      write(ptr,space18);
      ieee2real(valout,note8,realval);
      write(ptr,note8); write(ptr,realval);
      ieee_exp_man(valout,expval,manval);
      write(ptr,space6); write(ptr,expval,FIELD=>6);
      write(ptr,' '); write(ptr,manval);
      writeline(resfile,ptr);
      write(ptr,space6);
      noteout := " B inp "; write(ptr,noteout);
      valout := bval;          write(ptr,valout(63));
      write(ptr,' '); write(ptr,valout(62 downto 52)); 
      write(ptr,' '); write(ptr,valout(51 downto 0 ));
      writeline(resfile,ptr);
      write(ptr,space18);
      ieee2real(valout,note8,realval);
      write(ptr,note8); write(ptr,realval);
      ieee_exp_man(valout,expval,manval);
      write(ptr,space6); write(ptr,expval,FIELD=>6);
      write(ptr,' '); write(ptr,manval);
      writeline(resfile,ptr);
   end write_abinp;

   procedure write_expsig(signal gt,eq,lt,a0,a1,b0,b1: in BIT;
                          signal dist,lgr: in BIT_VECTOR) is
      variable ptr : LINE;
      variable noteout : STRING (1 to 10);
      variable vbit : BIT;
      variable vdist : BIT_VECTOR (5 downto 0);
      variable vlgr : BIT_VECTOR (10 downto 0);
   begin
      write(ptr,NOW,FIELD=>6);
      noteout := " exp >=< a"; write(ptr,noteout);
      noteout := "0&1 b0&1= "; write(ptr,noteout);
      vbit := gt;  write(ptr,vbit);
      vbit := eq;  write(ptr,vbit);
      vbit := lt;  write(ptr,vbit);
      vbit := a0;  write(ptr,vbit);
      vbit := a1;  write(ptr,vbit);
      vbit := b0;  write(ptr,vbit);
      vbit := b1;  write(ptr,vbit);
      noteout := " SHF-DIST="; write(ptr,noteout);
      vdist := dist;  write(ptr,vdist);
      noteout := "  LGR-EXP="; write(ptr,noteout);
      vlgr := lgr;  write(ptr,vlgr);
      writeline(resfile,ptr);
   end write_expsig;

   procedure write_mansig(signal gt,eq,lt,a0,b0: in BIT) is
      variable ptr : LINE;   
      variable noteout : STRING (1 to 21);
      variable vbit : BIT;
   begin
      write(ptr,NOW,FIELD=>6);
      noteout := " man csig >=< a0 b0= "; write(ptr,noteout);
      vbit := gt;  write(ptr,vbit); 
      vbit := eq;  write(ptr,vbit);
      vbit := lt;  write(ptr,vbit);
      vbit := a0;  write(ptr,vbit);
      vbit := b0;  write(ptr,vbit);
      writeline(resfile,ptr);
   end write_mansig;

   procedure write_xbar(signal swap: in BIT; signal xbarr,xbarl: in BIT_VECTOR)
   is
      variable ptr : LINE;
      variable noteout : STRING (1 to 7);
      variable vbit : BIT;
      variable vout : BIT_VECTOR (52 downto 0);
   begin
      write(ptr,NOW,FIELD=>6);
      noteout := " XBARS "; write(ptr,noteout);
      vbit := swap; write(ptr,vbit);
      noteout := " LEFT  "; write(ptr,noteout);
      vout:= xbarl; write(ptr,vout(52));
      write(ptr,'.'); write(ptr,vout(51 downto 0));
      writeline(resfile,ptr);
      write(ptr,space6);
      write(ptr,space8);
      noteout := " RIGHT "; write(ptr,noteout);
      vout:= xbarr; write(ptr,vout(52));
      write(ptr,'.'); write(ptr,vout(51 downto 0));
      writeline(resfile,ptr);
   end write_xbar;

   procedure write_inmux(signal rnan,lzero: in BIT;
                         signal rout,lout: in BIT_VECTOR) is
      variable ptr : LINE;
      variable noteout : STRING (1 to 7);
      variable vbit : BIT; 
      variable vout : BIT_VECTOR (52 downto 0);
   begin 
      write(ptr,NOW,FIELD=>6);
      noteout := " ZEROS "; write(ptr,noteout);
      vbit := lzero; write(ptr,vbit);
      noteout := " mux L "; write(ptr,noteout);
      vout := lout; write(ptr,vout(52));
      write(ptr,'.'); write(ptr,vout(51 downto 0));
      writeline(resfile,ptr);
      write(ptr,space6);
      noteout := " NAN S "; write(ptr,noteout);
      vbit := rnan; write(ptr,vbit);
      noteout := " mux R "; write(ptr,noteout);
      vout := rout; write(ptr,vout(52));
      write(ptr,'.'); write(ptr,vout(51 downto 0));
      writeline(resfile,ptr);
   end write_inmux;

   procedure write_shf(signal dist:in BIT_VECTOR;signal shfout:in BIT_VECTOR)
   is
      variable ptr : LINE;
      variable noteout : STRING (1 to 7);
      variable shfdist : INTEGER;
      variable vout : BIT_VECTOR (56 downto 0);
   begin
      write(ptr,NOW,FIELD=>6);
      noteout := " Sdist="; write(ptr,noteout);
      write(ptr,bit2int(dist));
      writeline(resfile,ptr);
      write(ptr,space6); write(ptr,space8);
      noteout := " S out "; write(ptr,noteout);
      vout := shfout; write(ptr,vout(56));
      write(ptr,'.'); write(ptr,vout(55 downto 0));
      writeline(resfile,ptr);
   end write_shf;

   procedure write_twoscompout(signal twoscomp : in BIT;
                               signal ladderin,radderin : in BIT_VECTOR) is
      variable ptr : LINE;
      variable noteout : STRING (1 to 7);
      variable note6 : STRING (1 to 6);
      variable vbit : bit;
      variable vout : BIT_VECTOR (57 downto 0);
   begin
      write(ptr,NOW,FIELD=>6);
      noteout := " COMP ="; write(ptr,noteout);
      vbit := twoscomp;     write(ptr,vbit);
      note6 := " lain "; write(ptr,note6);
      vout := ladderin; write(ptr,vout(57 downto 56));
      write(ptr,'.');   write(ptr,vout(55 downto 0));
      writeline(resfile,ptr);
      write(ptr,space6); write(ptr,space8);
      note6 := " rain "; write(ptr,note6);
      vout := radderin; write(ptr,vout(57 downto 56));
      write(ptr,'.');   write(ptr,vout(55 downto 0));
      writeline(resfile,ptr);
   end write_twoscompout;

   procedure write_adderout(signal addersum : in BIT_VECTOR) is
      variable ptr : LINE;
      variable noteout : STRING (1 to 13);
      variable vout : BIT_VECTOR (58 downto 0);
   begin
      write(ptr,NOW,FIELD=>6);
      noteout := " ADDERoutput "; write(ptr,noteout);
      vout := addersum; write(ptr,vout(58 downto 56));
      write(ptr,'.');   write(ptr,vout(55 downto 0));
      writeline(resfile,ptr);
   end write_adderout;

   procedure write_adderoutsig(signal dec1,dec2,fract0 : in BIT;
                               signal leading1pos : in BIT_VECTOR) is
      variable ptr : LINE;
      variable noteout : STRING (1 to 10);
      variable vbit : BIT;
      variable vdist : INTEGER;
      variable vout : BIT_VECTOR (5 downto 0);
   begin
      write(ptr,NOW,FIELD=>6);
      noteout := " ADD out s"; write(ptr,noteout);
      noteout := "igs 2-1-fr"; write(ptr,noteout);
      vbit := dec1; write(ptr,vbit);
      vbit := dec2; write(ptr,vbit);
      vbit := fract0; write(ptr,vbit);
      noteout := "  LD1pos  "; write(ptr,noteout);
      vout := leading1pos; write(ptr,vout);
      vdist := bit2int (vout); write(ptr,'='); write(ptr,vdist);
      writeline(resfile,ptr);
   end write_adderoutsig;

   procedure write_exp_choices(signal plus,larger : in BIT_VECTOR;
                               signal adjusted    : in BIT_VECTOR) is
      variable ptr : LINE;
      variable noteout : STRING (1 to 12);
      variable vout : BIT_VECTOR (10 downto 0);
      variable vout12 : BIT_VECTOR (11 downto 0);
   begin
      write(ptr,NOW,FIELD=>6);
      noteout := " exp plus 1 "; write(ptr,noteout);
      vout := plus; write(ptr,vout);
      noteout := "     larger "; write(ptr,noteout);
      vout := larger; write(ptr,vout);
      noteout := "   adjusted "; write(ptr,noteout);
      vout12 := adjusted; vout := vout12(10 downto 0); write(ptr,vout);
      writeline(resfile,ptr);
   end write_exp_choices;

   procedure write_normalized(signal sign : BIT;
                              signal exponent : BIT_VECTOR;
                              signal mantissa : BIT_VECTOR)
   is
      variable ptr : LINE;
      variable noteout : STRING (1 to 7);
      variable note8 : STRING (1 to 8);
      variable vsign : BIT;
      variable vexp : BIT_VECTOR (10 downto 0);
      variable vman : BIT_VECTOR (57 downto 0);
      variable ieeebitrep : BIT_VECTOR (63 downto 0);
      variable realval,manval : REAL;
      variable expval : INTEGER;
   begin
      write(ptr,NOW,FIELD=>6);
      noteout := " NORML "; write(ptr,noteout);
      writeline(resfile,ptr); 
      write(ptr,space6);
      vsign := sign; write(ptr,vsign);
      vexp := exponent; write(ptr,' '); write(ptr,vexp);
      vman := mantissa; write(ptr,' '); write(ptr,vman(57 downto 56));
      write(ptr,'.'); write(ptr,vman(55 downto 0));
      writeline(resfile,ptr);
      write(ptr,space18);
      ieeebitrep := vsign & vexp & vman(55 downto 4);
      ieee2real(ieeebitrep,note8,realval);
      ieee_exp_man(ieeebitrep,expval,manval);
      write(ptr,note8); write(ptr,realval);
      write(ptr,space6); write(ptr,expval,FIELD=>6);
      write(ptr,' '); write(ptr,manval);
      writeline(resfile,ptr);
   end write_normalized;

   procedure write_rounded   (signal sign : BIT;
                              signal exponent : BIT_VECTOR;
                              signal mantissa : BIT_VECTOR)
   is
      variable ptr : LINE;
      variable noteout : STRING (1 to 15);
      variable note8 : STRING (1 to 8);
      variable vsign : BIT;
      variable vexp : BIT_VECTOR (10 downto 0);
      variable vman : BIT_VECTOR (52 downto 0);
      variable ieeebitrep : BIT_VECTOR (63 downto 0);
      variable realval,manval : REAL;
      variable expval : INTEGER;
   begin
      write(ptr,NOW,FIELD=>6);
      noteout := " ROUNDED VALUE "; write(ptr,noteout);
      writeline(resfile,ptr);
      write(ptr,space6);
      vsign := sign; write(ptr,vsign);
      vexp := exponent; write(ptr,' '); write(ptr,vexp);
      vman := mantissa; write(ptr,' '); write(ptr,vman(52));
      write(ptr,'.'); write(ptr,vman(51 downto 0));
      writeline(resfile,ptr);
      write(ptr,space18);
      ieeebitrep := vsign & vexp & vman(51 downto 0);
      ieee2real(ieeebitrep,note8,realval);
      ieee_exp_man(ieeebitrep,expval,manval);
      write(ptr,note8); write(ptr,realval);
      write(ptr,space6); write(ptr,expval,FIELD=>6);
      write(ptr,' '); write(ptr,manval);
      writeline(resfile,ptr);
      write(ptr,' '); writeline(resfile,ptr);
   end write_rounded;

   procedure write_final   (signal sign : BIT;
                            signal exponent : BIT_VECTOR;
                            signal mantissa : BIT_VECTOR;
                            signal flags : BIT_VECTOR)
   is
      variable ptr : LINE;
      variable noteout : STRING (1 to 15);
      variable note8 : STRING (1 to 8);
      variable vsign : BIT;
      variable vexp : BIT_VECTOR (10 downto 0);
      variable vman : BIT_VECTOR (52 downto 0);
      variable vflags : BIT_VECTOR (0 to 6);
      variable ieeebitrep : BIT_VECTOR (63 downto 0);
      variable realval,manval : REAL;
      variable expval : INTEGER;
   begin
      write(ptr,NOW,FIELD=>6);
      noteout := " FINAL VALUE   "; write(ptr,noteout);
      noteout := "Z O N Os D X V "; write(ptr,noteout);
      vflags := flags; write(ptr,vflags);
      writeline(resfile,ptr);
      write(ptr,space6);
      vsign := sign; write(ptr,vsign);
      vexp := exponent; write(ptr,' '); write(ptr,vexp);
      vman := mantissa; write(ptr,' '); write(ptr,vman(52));
      write(ptr,'.'); write(ptr,vman(51 downto 0));
      writeline(resfile,ptr);
      write(ptr,space18);
      ieeebitrep := vsign & vexp & vman(51 downto 0);
      ieee2real(ieeebitrep,note8,realval);
      ieee_exp_man(ieeebitrep,expval,manval);
      write(ptr,note8); write(ptr,realval);
      write(ptr,space6); write(ptr,expval,FIELD=>6);
      write(ptr,' '); write(ptr,manval);
      writeline(resfile,ptr);
      write(ptr,' '); writeline(resfile,ptr);
   end write_final;

end print;
--**********************************************************************

--**********************************************************************
-- fpa.vhd
--------  VHDL Repository Prolog ------------
--
-- Unit name    : Floating Point Adder Test Bench
-- Version      : 1.0
-- Author       : Jo DeGroat
--              : Air Force Institute of Technology
-- DDN Address  : jdegroat@blackbird.afit.af.mil
-- Copyright    : (c) Air Force Institute of Technology
-- Date created : August 1988
-- Release date : June 15,1989
-- Last update  : June 15,1989
-- VHDL Version : IEEE Std 1076
-- Machine/System Analyzed/Simulated on: Simulated on VAX 11/785
--                using Intermetrics VHDL system, version 1.5b under VMS
---------------------------------------------------------------
-- Keywords     : Floating Point, Adder
-- Abstract     : This VHDL file is the adder description.  Details of the
--                exact algorithm used for floating point addition can
--                be obtained from the author.  It implements addition
--                of numbers in double precesion IEEE std 754 floating point
--                notation producing results in that notation.  I handles
--                overflow, underflow, denormalized number, infinity and
--                not-a-numbers as described in the standard.  It does not
--                recognize any NaN as signaling.
------------------ Revision history ---------------------------
-- DATE         VERSION AUTHOR       HISTORY
-- 15 June 89     1.0   Jo DeGroat   Initial Release
------------------ Distribution and Copyright -----------------
-- This prologue must be included in all copies of this VHDL code.
-- This description is copyright by the author.
-- This description is released to the VHDL community.
-- Restrictions on use or distribution:  NONE
------------------ Disclaimer ---------------------------------
-- This VHDL description code and its documentation are provided
-- "AS IS" and without any expressed or implied warranties
-- whatsoever.  No warranties as to performance, merchantability,
-- or fitness for a particular purpose exist.
--
-- Because of the diversity of conditions under which this code
-- may be used, no warranty of fitness for a particular purpose
-- is offered.  The user is advised to evaluate the code
-- thoroughly before relying on it.  The user must assume the
-- entire risk and liability of using this code.
--
-- In no event shall any person or organization of people be
-- held responsible for any direct, indirect, consequential
-- or inconsequential damages or lost profits.
-------------------END-PROLOG--------------------------------
entity FLOATING_POINT_ADDER is
port (A_Main:     in  BIT_VECTOR;
      B_Main:     in  BIT_VECTOR;
      C_Main:     out  BIT_VECTOR;
      A_Out:      out  BIT_VECTOR;
      Flags:      out BIT_VECTOR;
      Add_or_sub: in BIT;
      Latch:      in BIT;
      Drive:      in BIT;
      Phi1:       in BIT;
      Phi2:       in BIT;
      Asel:       in bit);
end FLOATING_POINT_ADDER;

use WORK.fparesc.all;
use WORK.print.all;
architecture MIXED of FLOATING_POINT_ADDER is
--
--  constants
--
   constant zeroexp : BIT_VECTOR (10 downto 0) := B"00000000000";
   constant oneexp  : BIT_VECTOR (10 downto 0) := B"11111111111";
   constant zeroman : BIT_VECTOR (51 downto 0) := X"0_0000_0000_0000";
   constant zero_56 : BIT_VECTOR (55 downto 0) := X"00_0000_0000_0000";
   constant zero_58 : BIT_VECTOR (57 downto 0) := "00" & X"00_0000_0000_0000";
   constant nanman  : BIT_VECTOR (52 downto 0) :=
         B"1_1000_00000000_00000000_00000000_00000000_00000000_00000001";
   constant zeroman53  : BIT_VECTOR (52 downto 0) :=
         B"0_0000_00000000_00000000_00000000_00000000_00000000_00000000";
--
-- internal control signals and other signals needed
--
   signal A_temp,B_temp : BIT_VECTOR (63 downto 0);
   signal A_inp,B_inp : BIT_VECTOR (63 downto 0);
   signal expgt,expeq,explt : BIT;
   signal expa0,expa1,expb0,expb1 : BIT;
   signal mangt,maneq,manlt : BIT;
   signal mana0,manb0 : BIT;
   signal shiftdist : BIT_VECTOR (5 downto 0);
   signal larger_exp : BIT_VECTOR (10 downto 0);
   signal adenorm,bdenorm : BIT;
   signal lshfa,lshfb,lxbarin,rxbarin : BIT_VECTOR (52 downto 0);
   signal swap : BIT;
   signal xbar_r,xbar_l : BIT_VECTOR (52 downto 0);
   signal in_mux_r_nan,in_mux_l_zero : BIT;
   signal in_mux_r,in_mux_l : BIT_VECTOR (52 downto 0);
   signal shifted_sig : BIT_VECTOR (56 downto 0);
   signal twoscomp : BIT;
   signal ladderin,radderin : BIT_VECTOR (57 downto 0);
   signal adder_out :  BIT_VECTOR (58 downto 0);
   signal dec1,dec2,fract0 : BIT;
   signal lding1pos : BIT_VECTOR (5 downto 0);
   signal expp1all1,underflow,expadjall0,lgrall0 : BIT;
   signal lgexp_p1 : BIT_VECTOR (10 downto 0);
   signal lgexp_add_left,lgexp_add_right,exp_adjusted:BIT_VECTOR (11 downto 0);
   signal lshiftdist : BIT_VECTOR (5 downto 0);
   signal man_lshf,man_lshf_rs1,man_rshf : BIT_VECTOR (57 downto 0);
   signal exp_sel_p1,exp_sel_lgr,exp_sel_adj,exp_sel_0 : BIT;
   signal man_sel_ls,man_sel_ls_rs,man_sel_rs,man_sel_val,man_sel_0  : BIT;
   signal signout  : BIT;
   signal exp_norm : BIT_VECTOR (10 downto 0);
   signal man_norm : BIT_VECTOR (57 downto 0);
   signal lsb3zero,round,round_incr_exp : BIT;
   signal man_norm_p1,man_norm_trunc,man_round : BIT_VECTOR (52 downto 0);
   signal exp_norm_p1,exp_round : BIT_VECTOR (10 downto 0);
   signal exp_norm_p1_all1 :BIT;
   signal zero, overflow, nan, overshift, denorm, inexact, invalid : BIT;
   signal flag_temp : BIT_VECTOR (0 to 6);
--
--  aliases for ease of working
--
   alias signa : BIT is A_inp (63);
   alias expa  : BIT_VECTOR (10 downto 0) is A_inp (62 downto 52);
   alias mana  : BIT_VECTOR (51 downto 0) is A_inp (51 downto 0);
   alias signb : BIT is B_inp (63);
   alias expb  : BIT_VECTOR (10 downto 0) is B_inp (62 downto 52);
   alias manb  : BIT_VECTOR (51 downto 0) is B_inp (51 downto 0);
   alias signc : BIT is C_Main (63);
   alias expc  : BIT_VECTOR (10 downto 0) is C_Main (62 downto 52);
   alias manc  : BIT_VECTOR (51 downto 0) is C_Main (51 downto 0);
--
begin
--
--    ------------------------
--    latch inputs using a msff latch.  Latch into internal temp on Phi2
--        and latch input high.  Then drive internal structures on Phi1.
--
--    write_abbus(A_Main,B_Main);

   b1:block((Phi2 and Latch) = '1')
      begin
      A_temp <= guarded A_Main;
      B_temp(63) <= guarded Add_or_sub xor B_Main(63);
      B_temp(62 downto 0) <= guarded B_Main(62 downto 0);
   end block;
  
   b2:block(Phi1 = '1')
      begin
      A_inp <= guarded A_temp;
      B_inp <= guarded B_temp;
   end block;
  
-- write_abinp(A_inp,B_inp);
--
--    -----------------------------
--    exponent processing and internal control signal generation
--
   expgt <= '1' when (expa > expb) else '0';
   expeq <= '1' when (expa = expb) else '0';
   explt <= '1' when (expa < expb) else '0';
   expa0 <= '1' when (expa = zeroexp) else '0';
   expa1 <= '1' when (expa = oneexp ) else '0';
   expb0 <= '1' when (expb = zeroexp) else '0';
   expb1 <= '1' when (expb = oneexp ) else '0';
   shiftdist <= expdist(expa,expb);
   larger_exp <= expa when (expa >= expb) else expb;
-- write_expsig(expgt,expeq,explt,expa0,expa1,expb0,expb1,shiftdist,larger_exp);
--
-- mantissa processing for generation of internal signals
--
   mangt <= '1' when (mana > manb) else '0';
   maneq <= '1' when (mana = manb) else '0';
   manlt <= '1' when (mana < manb) else '0';
   mana0 <= '1' when (mana = zeroman) else '0';
   manb0 <= '1' when (manb = zeroman) else '0';
-- write_mansig(mangt,maneq,manlt,mana0,manb0);
--
-- Muxes to check for denormalized numbers and left shift them by 1
-- else prepend a 0 or 1 to all others.
--
   adenorm <= expa0 and (not mana0);
   bdenorm <= expb0 and (not manb0);
   lshfa(52 downto 1) <= mana; lshfa(0) <= '0';
   lshfb(52 downto 1) <= manb; lshfb(0) <= '0';
   lxbarin <= lshfa when (adenorm = '1') else ((not expa0) & mana);
   rxbarin <= lshfb when (bdenorm = '1') else ((not expb0) & manb);
--
-- 2x2 crossbar placing larger number's mantissa on right path
-- 
--
   swap <= expgt or (expeq and mangt);
   xbar_r <= lxbarin when (swap = '1') else rxbarin;
   xbar_l <= rxbarin when (swap = '1') else lxbarin;
-- write_xbar(swap,xbar_r,xbar_l);
--
-- choice of hard values for right and left when needed
--
-- nan for right when adding +inif and -inif
--
   in_mux_r_nan <= expa1 and mana0 and expb1 and manb0 and (signa xor signb);
   in_mux_r <= nanman when (in_mux_r_nan = '1') else xbar_r;
--
-- zero for left when nan or inif on right
-- 
   in_mux_l_zero <= expa1 or expb1;
   in_mux_l <= zeroman53 when (in_mux_l_zero = '1') else xbar_l;
-- write_inmux(in_mux_r_nan,in_mux_l_zero,in_mux_r,in_mux_l);
--
-- shifter for left hand side - this is a right shifter
-- that inserts leading 0's for shifted bits  -
-- input is the 53 bit value on the left path
-- output is a 57 bit value that includes 4 guard bits
--
   shifted_sig <= shift (shiftdist,in_mux_l);
-- write_shf(shiftdist,shifted_sig);
--
-- if the sign bits of a and b inputs are diffenent
-- select the inverse of the shifted signal and set the carry into
-- the adder to 1 - if the same use the signal and carry is 0
-- also add an extra bit so format is now xx.xxx-> xx for both
-- inputs to the adder (58 bit values)
--
   twoscomp <= signa xor signb;
   ladderin <= '0' & shifted_sig when (twoscomp = '0')
          else '1' & (not shifted_sig);
   radderin <= '0' & in_mux_r & "0000";
-- write_twoscompout(twoscomp,ladderin,radderin);
--
-- adder to add the two values
--
   adder_out <= csadd(ladderin,radderin,twoscomp);
-- write_adderout(adder_out);
--
-- ****************** NORMALIZATION CIRCUITRY *******************
-- generation of control signals on adder output
-- need to know if fractional part is all 0's
-- if either bit to the left of the binary point is 0 or 1
-- and the position of the leading 1 in the fractional part
--
   dec1 <= adder_out(56);
   dec2 <= adder_out(57);
   fract0 <= '1' when (adder_out(55 downto 0) = zero_56) else '0';
   lding1pos <= leadingone(adder_out(55 downto 0));
-- write_adderoutsig(dec2,dec1,fract0,lding1pos);
--
-- processing of larger exponent
-- need a increment and an all 1's indication for the increment
-- need the differnece with the leading ones position with
--   an underflow indication
--
   lgexp_p1 <= expincr (larger_exp);
   expp1all1 <= '1' when (lgexp_p1 = oneexp) else '0';
--
   lgexp_add_left <= '0' & larger_exp;
   lgexp_add_right <= "111111" & not lding1pos;
   exp_adjusted <= lgexpadder (lgexp_add_left,lgexp_add_right);
   underflow <= exp_adjusted(11);
   lgrall0 <= expa0 and expb0;
   expadjall0 <= '1' when (exp_adjusted = "000000000000") else '0';
-- write_exp_choices(lgexp_p1,larger_exp,exp_adjusted);
--
-- generation of mantissa choices - need a value right shifted one
-- and a value left shifted by the smaller of lding1pos or the larger_exp
-- when the larger_exp is smaller as indicated by the underflow.
-- also need the result of the left shift right shifted one for 
--  denormoralized outputs
--
   lshiftdist <= larger_exp(5 downto 0) when (underflow = '1')
                                        else lding1pos;
   man_lshf <= leftshift(adder_out,lshiftdist);
   man_lshf_rs1 <= '0' & man_lshf (57 downto 1);
   man_rshf <= '0' & adder_out (57 downto 1);
-- 
-- generation of exponent select signals for the 4 to 1 mux
--
   exp_sel_p1  <= dec2;
   exp_sel_lgr <= (not dec2) and dec1;
   exp_sel_adj <= (not dec2) and (not dec1)
                             and (not fract0) and (not underflow);
   exp_sel_0   <= (((not dec2) and (not dec1) and fract0) or
                   ((not dec2) and (not dec1) and (not fract0) and underflow));
--
-- generation of mantissa select signals for the 4 to 1 mux
-- 
   man_sel_ls   <= (not dec2) and (not dec1) and (not(underflow or expadjall0));
   man_sel_ls_rs <= (not dec2) and (not dec1) and (underflow or expadjall0);
   man_sel_rs    <= (dec2 and (not expp1all1)) or
                         ((not dec2) and dec1 and lgrall0);
   man_sel_val   <= (not dec2) and dec1 and (not lgrall0);
   man_sel_0     <= dec2 and expp1all1;
--
-- output of normalization multiplexors;
--
   exp_norm <= lgexp_p1                  when (exp_sel_p1  = '1') else
               larger_exp                when (exp_sel_lgr = '1') else
               exp_adjusted(10 downto 0) when (exp_sel_adj = '1') else
               zeroexp;
--
   man_norm <= man_lshf  (57 downto 0)    when (man_sel_ls  = '1')   else
               man_lshf_rs1 (57 downto 0) when (man_sel_ls_rs = '1') else
               adder_out (57 downto 0)    when (man_sel_val = '1')   else
               man_rshf  (57 downto 0)    when (man_sel_rs  = '1')   else
               zero_58;
--
-- output sign
--
   signout <= signa   when (swap = '1') else  signb;
-- write_normalized(signout,exp_norm,man_norm);
--
-- ********************** ROUNDING UNIT design *******************
-- will use round to nearest as defined in the standard
-- 
   lsb3zero <= man_norm(2) or man_norm(1) or man_norm(0);
   round    <= ((lsb3zero and man_norm(3))
                  or ((not lsb3zero) and man_norm(3) and man_norm(4)));
   man_norm_trunc <= man_norm (56 downto 4);
   man_norm_p1 <= manincr(man_norm_trunc);
   man_round   <= man_norm_p1 when (round = '1') else man_norm_trunc;
   exp_norm_p1 <= expincr(exp_norm);
   exp_norm_p1_all1 <= '1' when (exp_norm_p1 = oneexp) else '0';
   round_incr_exp <= round and (man_norm_trunc(52) xor man_norm_p1(52));
   exp_round <= exp_norm_p1 when (round_incr_exp = '1') else exp_norm;
-- write_rounded(signout,exp_round,man_round);
--
-- ************************ FLAG GENERATION ***********************
-- Generation of output signal flags 
-- Flags included are zero, overflow, Not a Number (NaN) result, 
--    overshift (shift of 111111), denormalized, inexact (rounded result)
--    and invalid (+inif + -inif) which is illegal
--
   zero <= (not dec2) and (not dec1) and fract0;
   overflow <= man_sel_0 or (round_incr_exp and exp_norm_p1_all1);
   nan <= (expa1 and (not mana0)) or (expb1 and (not manb0)) or invalid;
   overshift <= '1' when (shiftdist = "111111") else '0';
   denorm <= (man_sel_ls_rs and (not fract0))
                           or ((not dec2) and dec1 and lgrall0);
   inexact <= round;
   invalid  <= in_mux_r_nan;
   flag_temp <= zero & overflow & nan & overshift & denorm &
                          inexact & invalid;
--
-- *********************** DRIVING OF OUTPUT LATCH *****************
-- Latch flags whenever drive is high during Phi2
-- Latch result onto C_Main whenever drive high during Phi2 and not Aselect
-- Latch result onto A_bus whenever drive high during Phi2 and Aselect
--
   out_latch1 : block ((Drive and Phi2) = '1')
   begin
      Flags <= guarded flag_temp;
   end block out_latch1;

   out_latch2 : block ((Drive and Phi2 and (not Asel)) = '1')
   begin
      C_Main <= guarded signout & exp_round & man_round(51 downto 0);
   end block out_latch2;

   out_latch3 : block ((Drive and Phi2 and Asel) = '1')
   begin
      A_out <= guarded signout & exp_round & man_round(51 downto 0);
   end block out_latch3;
--
-- ************************ write final results **********************
--
-- Input/Output check process
   process
   begin
      wait until ((Phi2 = '1') and (not Phi2'stable) and (Drive = '1'));
      wait until ((Phi2 = '0') and (not Phi2'stable));
      write_abinp(A_inp,B_inp);
      write_final(signout,exp_round,man_round,flag_temp);
   end process;
--
--

end MIXED;
--**********************************************************************

--**********************************************************************
-- bench.vhd
--------  VHDL Repository Prolog ------------
--
-- Unit name    : Floating Point Adder Test Bench
-- Version      : 1.0
-- Author       : Jo DeGroat
--              : Air Force Institute of Technology
-- DDN Address  : jdegroat@blackbird.afit.af.mil
-- Copyright    : (c) Air Force Institute of Technology
-- Date created : August 1988
-- Release date : June 15,1989
-- Last update  : June 15,1989
-- VHDL Version : IEEE Std 1076
-- Machine/System Analyzed/Simulated on: Simulated on VAX 11/785
--                using Intermetrics VHDL system, version 1.5b under VMS
---------------------------------------------------------------
-- Keywords     : Floating Point, Adder
-- Abstract     : This VHDL file is the testbench for the
--                floating point adder.  It supplies the bus signals
--                and inputs required by the adder, invoking the adder
--                through component instantiation.  The entire VHDL
--                description for the adder consists of several files
--                   * bench.vhd - the test bench
--                   * fpa.vhd   - the description of the adder
--                   * fparesc.vhd - support routines for the adder
--                   * print.vhd - textio routines for testing the adder
--                   * typeconv.vhd - type conversion routines to aid
--                         development and testing of the description
--                   * abusvect - values for the A bus inputs
--                   * bbusvect - values for the B bus inputs
--                   * cntrlvect - values for the control bus
--                   * commands - commands and order for the description
--                   * results - results of textio output for a simulation
--                All vhdl and vect files are required for a vhdl simulation
--                of the system.  They should be analyzed, model generated
--                and built based on their dependencies as indicated in
--                the the commands file which is included.
--                Note that the vector files and results file have no Prolog
--                as they are support data files and must be used as given.
------------------ Revision history ---------------------------
-- DATE         VERSION AUTHOR       HISTORY
-- 15 June 1989   1.0   Jo DeGroat   Initial Release
------------------ Distribution and Copyright -----------------
-- This prologue must be included in all copies of this VHDL code.
-- This description is copyright by the author.
-- This description is released to the VHDL community.
-- Restrictions on use or distribution:  NONE
------------------ Disclaimer ---------------------------------
-- This VHDL description code and its documentation are provided
-- "AS IS" and without any expressed or implied warranties
-- whatsoever.  No warranties as to performance, merchantability,
-- or fitness for a particular purpose exist.
--
-- Because of the diversity of conditions under which this code
-- may be used, no warranty of fitness for a particular purpose
-- is offered.  The user is advised to evaluate the code
-- thoroughly before relying on it.  The user must assume the
-- entire risk and liability of using this code.
--
-- In no event shall any person or organization of people be
-- held responsible for any direct, indirect, consequential
-- or inconsequential damages or lost profits.
-------------------END-PROLOG--------------------------------
-- "Bench tester" for Floating point adder for VHDL version 1076
-- initiated Aug 88  V.0 R 0.0.3
--
entity BENCH_FPA  is
end BENCH_FPA;
--
--
library STD,WORK;
use STD.simulator_standard.all;
use STD.TEXTIO.all;
use WORK.fparesc.all;
architecture MIXED of BENCH_FPA is
--
--  Model stuff
--
signal A_BUS,B_BUS,C_BUS,A_ALT: BIT_VECTOR (63 downto 0);
signal Flag_Bus: BIT_VECTOR (0 to 6);
signal Add_or_sub,Latch,Drive: BIT;
signal Phi1: BIT;
signal Phi2: BIT;
signal Asel: BIT;
signal Precharge : BIT;
--
--
component FLOATING_POINT_ADDER
    port (A_Main:     in  BIT_VECTOR ;
          B_Main:     in  BIT_VECTOR ;
          C_Main:     out  BIT_VECTOR ;
          A_Out:      out  BIT_VECTOR;
          Flags:      out BIT_VECTOR ;
          Add_or_sub: in BIT;
          Latch:      in BIT;
          Drive:      in BIT;
          Phi1:       in BIT;
          Phi2:       in BIT;
          Asel:       in bit);
end component;
--
for all : FLOATING_POINT_ADDER use entity work.FLOATING_POINT_ADDER (MIXED);
--
--
BEGIN
--
--  Test bench control
--
   p1:process
      begin
      set_maximums(5000000,1000);
      tracing_on;
      wait;
   end process p1;
--
-- -------------------
-- CLOCK ASSIGNMENT
--
   clkproc: process
      -- this clock is for Phi1 and Phi2 for the ASP
      -- Phi1 is high for 10ns low for 30ns
      -- Phi2 is high for 20ns low for 20ns
      -- and rises 8ns after Phi1 drops
      begin
      wait for 2 ns;
      Phi1 <= '1';
      Precharge <= '1' after 2ns, '0' after 13ns;
      wait for 10 ns;
      Phi1 <= '0';
      wait for 8 ns;
      Phi2 <= '1';
      wait for 20 ns;
      Phi2 <= '0';
   end process clkproc;
--
-- -------------------
-- read file process
-- this process reads test vectors in from the
-- testvector files and sets up pseudo bus 
-- timing of all signals
--
   pread: process
--    file specification
--
      file abusvectors : TEXT is in "abusvect";
      file bbusvectors : TEXT is in "bbusvect";
      file cntrlvectors : TEXT is in "cntrlvect";
--
      variable L : Line;
      variable temp : BIT_VECTOR(63 downto 0);
      variable ctrltemp : BIT_VECTOR(1 to 4);
      constant High_64_bit : BIT_VECTOR(63 downto 0) := X"FFFF_FFFF_FFFF_FFFF";
--
     begin
      wait until ((Precharge = '1') and (not Precharge'stable));
      A_Bus <= High_64_bit;
      B_Bus <= High_64_bit;
      Latch <= '0'; Drive <= '0'; Asel  <= '0';
      wait until ((Precharge = '0') and (not Precharge'stable));
      readline(cntrlvectors,L);
      read (L, ctrltemp);
      Asel <= ctrltemp(1);
      Add_or_sub <= ctrltemp(2);
      Latch <= ctrltemp(3);
      Drive <= ctrltemp(4);
      if (ctrltemp(3) = '1') then
         readline(abusvectors,L);
         read (L, temp);
         A_Bus <= temp;
         readline(bbusvectors,L);
         read (L, temp);
         B_Bus <= temp;
      end if;
      if (ENDFILE(abusvectors) or ENDFILE(bbusvectors) or
           ENDFILE(cntrlvectors)) then wait for 100ns; terminate; end if;
   end process pread;
--
-- ---------------------
--  Instantiation of component

   A000:FLOATING_POINT_ADDER port map (A_BUS,B_BUS,C_BUS,A_ALT,Flag_Bus,
                           Add_or_sub,Latch,Drive,Phi1,Phi2,Asel);
--
end MIXED;

--**********************************************************************