--******************************************************************** -- Copyright (C) 1992 - University of Pittsburgh, Dept. Elect. Engr. -- PICALAB: Pittsburgh Integrated Circuits Analysis Laboratory --******************************************************************** -- Title: 4-bit serial Adder -- Created: Jan. 15, 1992 -- Written by: Jiyong Ahn -- MS Program Student -- -- Compile command : -- vcomp -e adder.adder_data s_adder.vhdl -- After executing above command, s_adder.ivf will be created. -- -- Description: -- This file contains entity and architecture descriptions -- for serial adder. -- D-Latch is first built and Flipflop is built based -- on D-Latch. And again, Register is built on Flipflop -- as the same hierarchical manner. -- Block commands are used to simulate Dynamic circuit -- behavior along with guarded statement to simulate -- precharged '1' state for carry and sum logic part. -- During the evaluation period, these circuits evaluate -- input values. -- Since D-Latch forms the basic part of Flipflop and -- Register, Only D-Latch part has block and guarded -- statement to simulate clocked circuit behaviour. --******************************************************************** -- ------------------------------------------------------- -- Description below is about clocked D-Latch. -- This block uses block statement to simulate -- clocked circuit. -- -- Legend> -- dlin : input for D-Latch -- lclock: clock input for D-Latch -- lreset: reset for D-Latch -- dlout : output of D-Latch -- dloutbar = (dlout)' ------------------------------------------------------- entity D_LATCH is port(dlin,lclock,lreset :in bit; dlout,dloutbar :out bit); end D_LATCH; architecture d_data of D_LATCH is begin block (lclock) begin dlout <= guarded "0" when lreset else dlin; end block; block (not lclock) begin dlout <= guarded "0" when lreset else dlout; end block; dloutbar <= not dlout; end d_data; -- ------------------------------------------------------- -- Description below is about Masker-Slave D F/F! -- Master-Slave -- Legend> -- ffin: input for F/F -- fclock: clock input for F/F -- freset: reset for F/F -- ffout: output of F/F -- ffoutbar = (ffout)' ------------------------------------------------------- entity MS_D_FF is port (ffin,fclock,freset: in bit; ffout,ffoutbar: out bit); end MS_D_FF; architecture ms_data of MS_D_FF is signal q0,q0bar,fclockbar:bit; label dl0,dl1; -- dl0: first stage latch in F/F -- dl1: second stage latch in F/F component D_LATCH port(dlin,lclock,lreset:in bit; dlout,dloutbar:out bit); end component; for dl0,dl1:D_LATCH use entity D_LATCH(d_data); begin dl0:D_LATCH port map (ffin,fclock,freset,q0,q0bar); fclockbar <= not(fclock); dl1:D_LATCH port map (q0,fclockbar,freset,ffout,ffoutbar); end ms_data; -- ------------------------------------------------------- -- Statement below describes 4-bit shift register -- Legend> -- regin: input for register -- rclock: you know... -- rreset: . -- regout: . ------------------------------------------------------- entity REG is port (regin,rclock,rreset: in bit; regout,regoutbar: out bit); end REG; architecture reg_data of REG is signal fq0,fq0bar,fq1,fq1bar,fq2,fq2bar:bit; -- fq0: first stage F/F output -- fq1: second . -- fq2: third . label ff0,ff1,ff2,ff3; -- ff0 to ff3: each stage of F/Fs in a register. component MS_D_FF port (ffin,fclock,freset:in bit; ffout,ffoutbar:out bit); end component; for ff0,ff1,ff2,ff3:MS_D_FF use entity MS_D_FF(ms_data); begin ff0:MS_D_FF port map (regin,rclock,rreset,fq0,fq0bar); ff1:MS_D_FF port map (fq0,rclock,rreset,fq1,fq1bar); ff2:MS_D_FF port map (fq1,rclock,rreset,fq2,fq2bar); ff3:MS_D_FF port map (fq2,rclock,rreset,regout,regoutbar); end reg_data; -- ------------------------------------------------------- -- Following describes about Sum logic block. -- Here again, block statement is used. -- Variable names are quite straight forward, I guess. -- Legend> -- a: addend input -- b: adder input -- cin: carry in from the last stage. -- sclock: clock input for SUM logic -- sum: output ------------------------------------------------------- entity SUM is port (a,b,cin,sclock: in bit; sum: out bit); end SUM; architecture sum_data of SUM is begin block (sclock) begin sum <= guarded (a xor b xor cin); end block; block (not sclock) begin sum <= guarded "1"; end block; end sum_data; -- ------------------------------------------------------- -- Carry logic block. Also, block statement is used. -- Legend> -- a: addend input -- b: adder input -- cin: carry in -- cclock: clock input -- cout: carry out ------------------------------------------------------- entity CARRY is port (a,b,cin,cclock: in bit; cout: out bit); end CARRY; architecture carry_data of CARRY is begin block (cclock) begin cout <= guarded ((a or b) and cin) or (a and b); end block; block (not cclock) begin cout <= guarded "1"; end block; end carry_data; -- ------------------------------------------------------- -- This is the real part.... -- Following description integrates adder circuit -- using components described above. -- Legend> -- a: addend input -- b: adder input -- phi1: clock #1 of the two phased clocks -- phi2: clock #2 which is 90 degrees out of -- phase from phi1. -- reset: reset input to the adder circuit -- sum: output 'sum' --> this is what you want. -- sumbar = (sum)' ------------------------------------------------------- entity adder is port(a,b,phi1,phi2,reset: in bit; sum,sumbar: out bit); end adder; architecture adder_data of adder is signal r0out,r0outbar,r1out,r1outbar,ff4out,ff4outbar,c0out,s0out:bit; label r0,r1,r2; component REG port(regin,rclock,rreset:in bit; regout,regoutbar:out bit); end component; for r0,r1,r2: REG use entity REG(reg_data); label ff4; component MS_D_FF port (ffin,fclock,freset:in bit; ffout,ffoutbar:out bit); end component; for ff4: MS_D_FF use entity MS_D_FF(ms_data); label s0; component SUM port(a,b,cin,sclock:in bit; sum:out bit); end component; for s0: SUM use entity SUM(sum_data); label c0; component CARRY port (a,b,cin,cclock:in bit; cout:out bit); end component; for c0: CARRY use entity CARRY(carry_data); begin r0: REG port map (a,phi2,reset,r0out,r0outbar); r1: REG port map (b,phi2,reset,r1out,r1outbar); c0: CARRY port map (r0out,r1out,ff4out,phi1,c0out); ff4: MS_D_FF port map (c0out,phi2,reset,ff4out,ff4outbar); s0: SUM port map (r0out,r1out,ff4out,phi1,s0out); r2: REG port map (s0out,phi2,reset,sum,sumbar); end adder_data; -- -------------------------- -- end of file --------------------------