DLXREGS consists of three sub-blocks : dlxregs_misc, mdr and the
interrupt block. The dlxregs_misc contains a set of registers which
are mainly used for forwarding; mdr block contains the data memory
interface and the associated registers like the LMDR, SMDR and the DMAR;
interrupt block contains the interrupt logic and includes the
registers interrupt mask (imsk) and the instruction address register
(IAR). Rsdout, Rs1out and Rs2out are the desitnation, source 1 and source
2 for the current instruction in the EXE stage. Rsdout is needed for MDR
forwarding checking while Rs1out and Rs2out are needed for ALU output
forwarding. Rsdout_a and Rsdout_b are the destination of the instruction
in the MEM and WRITE stage respetively. The 32-bit busses that enable
dlxregs to talk with data memory are Daddrbus and Databus. Daddrbus is an
output bus while Databus is bidirectional.