Designer FPGA Development System

Synopsys

• Using Synopsys Design Constraints (SDC) with Designer

ACTgen

• Optimal Datapath Generation Using ACTgen

CAE

Synopsys Design Compiler

• Minimizing Single Event Upset Effects Using Synopsys
  
  
  Synplicity Synplify

• Using Synplify to Design in Actel Radiation-Hardened FPGAs
  
  

  
  Silicon Explorer

• Using Silicon Explorer for System-level Debug